Method of error correction in MBC flash memory

• US 20070089034A1
• Filed: 01/11/2006
• Published: 04/19/2007
• Est. Priority Date: 10/13/2005
• Status: Active Grant

• Current Assignee: Ramot at Tel Aviv University Limited (Tel Aviv University)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Alrod, Idan, Lasser, Menahem, Sharon, Eran, Murin, Mark, Litsyn, Simon
• Granted Patent: US 7,681,109 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1072 in multilevel memories

Abstract

A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

Claims

1. A method of storing data in a Multi-Bit per Cell (MBC) flash memory, comprising the steps of:

(a) calculating error correction parity bits for a plurality of logical pages of data bits, wherein at least one of said error correction parity bits applies jointly to at least two of said logical pages; and

(b) programming the MBC flash memory with said data bits and said error correction parity bits, with at least one cell of the MBC flash memory being programmed with data bits from more than one of said at least two logical pages to which said at least one joint error correction parity bit applies.

2. The method of claim 1, wherein all said error correction parity bits apply to all said logical pages.

3. The method of claim 1, wherein said plurality includes more than two said logical pages, and wherein said calculating includes calculating said error correction parity bits jointly for at least two said logical pages but for fewer than all said logical pages.

4. The method of claim 1, wherein each cell of said flash memory that is programmed with said bits is programmed with as many of said bits as there are logical pages in said plurality of logical pages.

5. Given a Multi-Bit per Cell (MBC) flash memory programmed with data bits of a plurality of logical pages and with error correction parity bits calculated for the data bits, with at least one of the error correction parity bits applying jointly to at least two of the logical pages, and with at least one cell of the MBC flash memory being programmed with data bits from more than one of the at least two logical pages to which the at least one joint error correction bit applies:

a method of recovering the data bits, comprising the steps of;

(a) reading, from the MBC flash memory;

(i) the data bits of the at least two logical pages to which the at least one joint error correction parity bit applies, and

(ii) the error correction parity bits that apply to any of the at least two logical pages to which the at least one joint error correction parity bit applies; and

(b) correcting the data bits, as read from the MBC flash memory, in accordance with the error correction parity bits, as read from the MBC flash memory.

6. A controller, for a Multi-Bit per Cell (MBC) flash memory, that is operative to store, in the MBC flash memory, data bits of a plurality of logical pages by steps including calculating error correction parity bits for the data bits, with at least one error correction parity bit applying jointly to at least two of the logical pages, and with data bits from more than one of the at least two logical pages, to which the at least one joint error correction parity bit applies, being stored together in each of at least one cell of the MBC flash memory.

7. The controller of claim 6, wherein the controller is operative to provide the data bits to a host of a memory device that includes the controller and the MBC flash memory, by steps including:

(a) reading, from the MBC flash memory;

(i) the data bits of the at least two logical pages to which the at least one joint error correction parity bit applies, and

(ii) the error correction parity bits that apply to any of the at least two logical pages to which the at least one joint error correction parity bit applies; and

(b) correcting the data bits, as read from the MBC flash memory, in accordance with the error correction parity bits, as read from the MBC flash memory.

8. A memory device comprising:

(a) the controller of claim 6;

and

(b) a MBC flash memory that is controlled by the controller of claim 6.

9. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a Multi-Bit Per Cell (MBC) flash memory, the computer-readable code comprising:

(a) program code for calculating error correction parity bits for a plurality of logical pages of data bits to be stored in the MBC flash memory, wherein at least one of said error correction parity bits applies jointly to at least two of said logical pages; and

(b) program code for programming the MBC flash memory with said data bits and said error correction parity bits, with at least one cell of the MBC flash memory being programmed with data bits from more than one of said at least two logical pages to which said at least one joint error correction parity bit applies.

10. Given a Multi-Bit per Cell (MBC) flash memory programmed with data bits of a plurality of logical pages and with error correction parity bits calculated for said data bits, with at least one of the error correction parity bits applying jointly to at least two of the logical pages, and with at least one cell of the MBC flash memory being programmed with data bits from more than one of the at least two logical pages to which the at least one joint error correction bit applies:

a computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code comprising;

(a) program code for reading, from the MBC flash memory;

(i) the data bits of the at least two logical pages to which the at least one joint error correction parity bit applies, and

(ii) the error correction parity bits that apply to any of the at least two logical pages to which the at least one joint error correction parity bit applies; and

(b) program code for correcting the data bits, as read from the MBC flash memory, in accordance with the error correction parity bits, as read from the MBC flash memory.

11. A method of storing data in a Multi-Bit per Cell (MBC) flash memory, comprising the steps of:

(a) computing a joint Error Correction Code (ECC) codeword for at least two of a plurality of logical pages of data bits; and

(b) programming the MBC flash memory with said joint ECC codeword.

12. The method of claim 11, wherein said ECC is systematic.

13. The method of claim 11, wherein said ECC is non-systematic.

14. The method of claim 11, wherein said plurality includes more than two said logical pages, and wherein said computing is for fewer than all said logical pages.

15. The method of claim 11, wherein each cell of the MBC flash memory that is programmed with said joint ECC codeword is programmed with as many bits of said joint ECC codeword as said logical pages for which said joint ECC codeword was computed.

16. The method of claim 11, wherein each cell of said flash memory that is programmed with said joint ECC codeword is programmed with as many bits as said plurality of logical pages.

17. Given a Multi-Bit per Cell (MBC) flash memory programmed with a joint Error Correction Code (ECC) codeword computed for at least two of a plurality of logical pages of data bits:

a method of recovering the data bits, comprising the steps of;

(a) reading the joint ECC codeword from the flash memory; and

(b) recovering, from the joint ECC codeword as read from the flash memory, the data bits of the at least two logical pages from which the joint ECC codeword was computed.

18. A controller, for a Multi-Bit per Cell (MBC) flash memory, that is operative to store, in the MBC flash memory, data bits of a plurality of logical pages, by steps including computing a joint Error Correction Code (ECC) codeword for at least two of said logical pages.

19. The controller of claim 18, wherein the controller is operative to provide the data bits to a host of a memory device that includes the controlelr and the MBC flash memory, by steps including:

(i) reading the joint ECC codeword from the MBC flash memory; and

(ii) recovering, from the joint ECC codeword as read from the MBC flash memory, the data bits of the at least two logical pages from which the joint ECC codeword was computed.

20. A memory device comprising:

(a) the controller of claim 18;

and

(b) a MBC flash memory that is controlled by the controller of claim 18.

21. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a Multi-Bit Per Cell (MBC) flash memory, the computer-readable code comprising:

(a) program code for computing a joint Error Correction Code (ECC) codeword for at least two of a plurality of logical pages of data bits to be stored in the MBC flash memory; and

(b) program code for programming the MBC flash memory with said joint ECC codeword.

22. Given a Multi-Bit per Cell (MBC) flash memory programmed with a joint Error Correction Code (ECC) codeword computed for at least two of a plurality of logical pages of data bits:

a computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code comprising;

(a) program code for reading the joint ECC codeword from the flash memory; and

(b) program code for recovering, from the joint ECC codeword as read from the flash memory, the data bits of the at least two logical pages from which the joint ECC codeword was computed.