Imaging engine employing planar light illumination and linear imaging

• US 20070090191A1
• Filed: 07/12/2006
• Published: 04/26/2007
• Est. Priority Date: 11/24/2000
• Status: Active Grant

• Current Assignee: Metrologic Instruments Incorporated (Honeywell International Inc.)
• Original Assignee: Metrologic Instruments Incorporated (Honeywell International Inc.)
• Inventors: Zhu, Xiaoxun, Schnee, Michael, Knowles, C.
• Granted Patent: US 7,743,990 B2
• Time in Patent Office: Days
• US Class Current: 235/462.41
• CPC Class Codes: G06K 2207/1018 Source control
• CPC Class Codes: G06K 7/10732 Light sources
• CPC Class Codes: G06K 7/10752 Exposure time control

Abstract

An imaging engine includes a plurality of linear imaging arrays, image formation optics, at least one illumination module and supporting circuitry that are embodied within a modular engine housing. The plurality of linear imaging arrays and image formation optics are mounted on an optical bench (which is integral to the engine housing) and provide field of views corresponding to the plurality of linear image arrays. The at least one illumination module produces planar light illumination that substantially overlaps the field of views corresponding to the plurality of linear imaging arrays. The supporting circuitry includes: timing signal generation circuitry that supplies timing signals to the linear imaging arrays in order to read out the row image data produced by such arrays (such row image data may be read out at a constant line rate or at a variable line rate); illumination control circuitry that supplies current to the illumination sources in the at least one illumination module; analog-to-digital conversion circuitry, which optionally filters row data image signal supplied thereto (to remove unwanted noise components) and converts the row image data supplied thereto into digital form; and data buffering circuitry, for storing the digital row image data generated by the analog-to-digital conversion circuitry and communicating the row image data stored therein over a data communication bus. One linear image array (e.g., linear imaging array C) may have a variable line rate that is controlled by the timing signals supplied thereto such that the image capture operations performed by the one linear imaging array (e.g. linear imaging array C) maintain a substantially constant aspect ratio, to thereby compensate for aspect ratio distortions that result from variations in velocity of engine with respect to target object(s). The variable line rate is based upon velocity estimates derived from processing of the pixel data values of other linear imaging arrays disposed therein. The supporting circuitry may optionally include a line rate adjustment module, preferably realized as part of a programmed controller, that is operably coupled to timing signal generation circuitry and adjusts the variable line rate of the one linear image device (e.g., linear imaging array C); output illumination control module, preferably realized as part of the programmed controller, that is operably coupled to the illumination control circuitry and adjusts the optical power level and/or illumination time period for the illumination that overlaps one or more of the FOVs of the linear imaging arrays of the engine for speckle reduction/constant white levels; and/or imaging processing circuitry, operably coupled to the data buffering circuitry over the data communication bus, that realizes portions of image-based mechanisms/techniques for image velocity estimation, aspect ratio compensation, jitter estimation and compensation, bar code detection, OCR, and image lift.

Claims

1-31. -31. (canceled)

32. An imaging engine comprising:

a plurality of linear imaging arrays and image formation optics that provide field of views corresponding to the plurality of linear image arrays;

at least one illumination module that produces planar light illumination that substantially overlaps the field of views corresponding to the plurality of linear imaging arrays; and

supporting circuitry that operably cooperates with said plurality of linear image arrays and said at least one illumination module during operation of the imaging engine.

33. The imaging engine of claim 32, wherein said supporting circuitry includes timing signal generation circuitry that supplies timing signals to the linear imaging arrays in order to read out the row image data produced by such linear imaging arrays.

34. The imaging engine of claim 32, wherein said supporting circuitry includes illumination control circuitry that supplies current to illumination sources of the at least one illumination module.

35. The imaging engine of claim 32, wherein said supporting circuitry includes analog-to-digital conversion circuitry, which optionally filters row data image signal supplied thereto to remove unwanted noise components and converts the row image data supplied thereto into digital form.

36. The imaging engine of claim 32, wherein said supporting circuitry includes data buffering circuitry, for storing the digital row image data generated by the analog-to-digital conversion circuitry and communicating the row image data stored therein over a data communication bus.

37. The imaging engine of claim 32, wherein one linear imaging array has a variable line rate that is controlled by the timing signals supplied thereto such that the image capture operations performed by the one linear imaging array maintains a substantially constant aspect ratio, to thereby compensate for aspect ratio distortions that result from variations in velocity of engine with respect to target object(s).

38. The imaging engine of claim 37, wherein the he variable line rate is based upon velocity estimates derived from processing of the pixel data values of other linear imaging arrays disposed therein.

39. The imaging engine of claim 32, wherein said supporting circuitry includes a line rate adjustment module that is operably coupled to timing signal generation circuitry and adjusts the variable line rate of the one linear image device.

40. The imaging engine of claim 39, wherein said line rate adjustment module is realized as part of a programmed controller.

41. The imaging engine of claim 32, wherein said supporting circuitry includes an output illumination control module that is operably coupled to the illumination control circuitry and adjusts the optical power level and/or illumination time period for illumination that overlaps one or more of the FOVs of the linear imaging arrays of the engine, to thereby reduce speckle noise and/or provide constant white level.

42. The imaging engine of claim 41, wherein said output illumination control module is realized as part of a programmed controller.

43. The imaging engine of claim 32, wherein said supporting circuitry includes imaging processing circuitry, operably coupled to the data buffering circuitry over the data communication bus, that realizes portions of image-based mechanisms for at least one of:

image velocity estimation, aspect ratio compensation, jitter estimation and compensation, bar code detection, OCR, and image lift.

44. The imagine engine of claim 43, wherein said imaging processing circuitry comprises dedicated hardware selected from the group of:

one or more FPGAs, one or more CPLDs, one or more ASICs.

45. The imagine engine of claim 43, wherein said imaging processing circuitry comprises one or more digital signal processing engines and associated memory.

46. The imaging engine of claim 32, wherein said planar light illumination overfills said field of views over a range of working distances of the engine during sequential image capture operations.

47. The imaging engine of claim 32, wherein said planar light illumination is produced from at least one source of coherent illumination.

48. The imaging engine of claim 47, wherein said at least one source comprises at least one visible laser diode.

49. The imaging engine of claim 48, wherein said at least one source comprises a plurality of visible laser diodes.

50. The imaging engine of claim 32, wherein said planar light illumination is produced from at least one source of incoherent illumination.

51. The imaging engine of claim 50, wherein said at least one source comprises at least one light emitting diode.

52. The imaging engine of claim 51, wherein said at least one source comprises a plurality of light emitting diodes.

53. The imaging engine of claim 32, wherein said planar light illumination is produced by at least one planar light illumination module comprising an illumination source, at least one focusing lens element, and at least one cylindrical lens element integrated into a modular housing disposed within said engine housing.

54. The imaging engine of claim 53, wherein said illumination source comprises at least one source of coherent illumination.

55. The imaging engine of claim 54, wherein said at least one source comprises at least one visible laser diode.

56. The imaging engine of claim 55, wherein said at least one source comprises a plurality of visible laser diodes.

57. The imaging engine of claim 53, wherein said illumination source comprises at least one source of incoherent illumination.

58. The imaging engine of claim 57, wherein said at least one source comprises at least one light emitting diode.

59. The imaging engine of claim 58, wherein said at least one source comprises a plurality of light emitting diodes.

60. The imaging engine of claim 53, wherein said planar light illumination is produced by planar light illumination arrays disposed on opposite sides of said plurality of linear imaging arrays, each planar light illumination array comprising at least one planar light illumination module.

61. The imaging engine of claim 53, wherein said planar light illumination is produced by multiple planar light illumination modules that are spaced apart and oriented on an optical bench in a manner that produces a composite beam of planar light illumination with substantial uniform intensity distribution over a range of working distances of the imaging engine.

62. The imaging engine of claim 32, wherein said supporting circuitry is disposed on at least on printed circuit board integral to said engine housing.