Dram including a vertical surround gate transistor

• US 20070090363A1
• Filed: 07/25/2005
• Published: 04/26/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Abbott, Todd
• Granted Patent: US 7,768,051 B2
• Time in Patent Office: Days
• US Class Current: 257/68
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.

Claims

1. A DRAM memory device comprising:

a vertical transistor comprising a source, a drain, a surround gate, and a channel region;

a bit line electrically coupled to the drain of the vertical transistor, wherein the gate comprises a word line of the memory device; and

a capacitor electrically coupled to the source.

2. The DRAM of claim 1, wherein at least a portion of the drain is silicided to form a bit line contact.

3. The DRAM of claim 1, wherein the word line of the vertical transistor is silicided.

4. The DRAM of claim 1, wherein the DRAM has a feature size of less than about 4F².

5. The DRAM of claim 1, wherein the surround gate comprises a silicided gate and a polysilicon gate.

6. The DRAM of claim 1, wherein the bit line comprises material selected from the group comprising:

Tungsten, Aluminum, and Copper.

7. A 4F² DRAM comprising a vertical surround gate transistor.

8. The 4F² DRAM of claim 7, wherein the vertical surround gate transistor comprises a silicided gate and a polysilicon gate.

9. A method of manufacturing a DRAM memory device having a feature size of less than about 4F², the method comprising:

forming a vertical surround gate transistor comprising a source, a drain, a surround gate, and a channel region, wherein, the gate comprises a word line of the memory device;

forming a bit line so that the bit line is electrically coupled to the drain of the vertical transistor; and

forming a capacitor so that the capacitor is electrically coupled to the source.

10. The method of claim 9, further comprising siliciding the word line.

11. The method of claim 9, further comprising siliciding the bit line.

12. A DRAM memory device comprising:

a vertical transistor comprising a source, a drain, a gate, and a channel region;

wherein, at least a portion of the gate is silicided to form a word line contact of the memory device;

a bit line electrically coupled to the drain of the vertical transistor; and

a capacitor electrically coupled to the source.

13. The DRAM of claim 12, wherein the gate comprises a surround gate.

14. A method of forming a memory device having a vertical surround gate transistor, the method comprising:

forming a semiconductor substrate comprising a first layer having a first doping and a second layer above the first layer having a doping opposite the first doping;

forming a silicided drain contact in electrical contact with the second layer;

forming a dielectric layer on a portion of the silicided drain contact;

forming a vertically extending polysilicon gate on the dielectric layer;

forming a vertically extending silicided gate on the dielectric layer;

epitaxially growing a channel region on the second layer so that the polysilicon gate is sandwiched between the channel region and the silicided gate;

epitaxially growing a source region on the channel region so that a portion of the source region overlaps with the polysilicon gate; and

forming a capacitor in electrical contact with the source region.

15. The method of claim 14, wherein the first layer comprises a n-type semiconductor material and the second layer comprises a p-type semiconductor material.

16. The method of claim 14, wherein the first layer comprises a p-type semiconductor material and the second layer comprises a n-type semiconductor material.

17. The method of claim 14, wherein the memory device is DRAM.

18. The method of claim 14, wherein the silicided gate is electrically coupled to a wordline of the memory device.

19. The method of claim 14, wherein the silicided drain contact is electrically coupled to a bitline of the memory device.

20. The method of claim 19, wherein the bitline comprises material selected from the group comprising:

Tungsten, Aluminum, and Copper.