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Dram including a vertical surround gate transistor

  • US 20070090363A1
  • Filed: 07/25/2005
  • Published: 04/26/2007
  • Est. Priority Date: 07/25/2005
  • Status: Active Grant
First Claim
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1. A DRAM memory device comprising:

  • a vertical transistor comprising a source, a drain, a surround gate, and a channel region;

    a bit line electrically coupled to the drain of the vertical transistor, wherein the gate comprises a word line of the memory device; and

    a capacitor electrically coupled to the source.

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