CMOS devices with a single work function gate electrode and method of fabrication

• US 20070090416A1
• Filed: 09/28/2005
• Published: 04/26/2007
• Est. Priority Date: 09/28/2005
• Status: Abandoned Application

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Inventors: Jin, Been-Yih, Kavalieros, Jack, Datta, Suman, Chau, Robert, Doyle, Brian, Brask, Justin
• Application Number:
  US11/238,447
• Publication Number:
  US 20070090416A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

Claims

1. An device comprising:

a first transistor of a first type and a second transistor of a type complementary to said first transistor on a substrate, wherein a channel region of said first transistor has a band gap that is different than that of an adjacent semiconductor region and wherein a gate electrode of said first transistor has substantially the same work function as a gate electrode of said second transistor.

2. The device of claim 1, wherein said first type is pMOS and said complementary type is nMOS.

3. The device of claim 1, wherein said channel region of said first transistor has a band gap that is smaller than that of said adjacent semiconductor region.

4. The device of claim 1, wherein said channel region of said first transistor is comprises a silicon-germanium alloy region.

5. The device of claim 4, wherein said silicon-germanium alloy region has a thickness of about 5-300 angstroms.

6. The device of claim 1, wherein said first transistor and said second transistor have a threshold voltage magnitude less than about 0.7 V.

7. The device of claim 1, wherein said gate electrode of said first transistor and said gate electrode of said second transistor have a mid-gap work function between about 4.5 and 4.9 eV.

8. The device of claim 1, wherein said first transistor and said second transistor each further comprise a non-planar semiconductor body having a top surface and a pair of opposite sidewalls.

9. The device of claim 1, wherein said substrate is a silicon-on-insulator substrate.

10. An device, comprising:

a pMOS transistor and an nMOS transistor on a substrate, wherein said pMOS transistor and said nMOS transistor each further comprise;

a non-planar silicon body having a top surface and a pair of laterally opposite sidewalls;

a channel region, wherein said channel region of said pMOS transistor comprises a silicon-germanium cladding layer adjacent to said non-planar silicon body;

a gate insulator adjacent to said channel region, wherein said gate insulator has a dielectric constant above about 8;

a gate electrode adjacent to said gate insulator, wherein said gate electrode of said pMOS transistor and said gate electrode of said nMOS transistor have the same work function; and

a source region and a drain region on opposite sides of said gate electrode.

11. The device of claim 10, wherein said channel region of said pMOS transistor comprises an n-type channel impurity concentration between about 1e17 atoms/cmˆ

3 and about 1e18 atoms/cmˆ

3.

12. A method, comprising:

forming a first transistor and a second transistor on a substrate, wherein forming each of said first transistor and said second transistor further comprises;

forming a channel region, wherein said channel region of said first transistor has a band gap different than that of an adjacent semiconductor region;

forming a gate insulator adjacent to said channel region;

forming a gate electrode adjacent said gate insulator, wherein said gate electrode of said first transistor and said gate electrode of said second transistor have the same mid-gap work function; and

forming a source region and a drain region on opposite sides of said gate electrode.

13. The method of claim 12, wherein forming said channel region comprises forming a non-planar body by recessing a pair of isolation regions on said substrate.

14. The method of claim 12, wherein forming said channel region comprises forming a silicon-germanium alloy region adjacent to a silicon substrate.

15. The method of claim 12, wherein forming said gate electrode comprises configuring said gate electrode into a tri-gate structure.

16. The method of claim 12, wherein forming said gate electrode comprises blanket depositing a gate electrode material over said gate insulator of said first transistor and said second transistor, wherein said gate electrode material has a mid-gap work function;

and

defining said gate electrode material into said gate electrode by a subtractive etch process.

17. A method, comprising:

forming a first transistor and a second transistor on a substrate, wherein forming each of said first transistor and said second transistor further comprises;

forming a non-planar silicon body;

forming a channel region on said non-planar silicon body, wherein said channel region of said first transistor is comprised of silicon-germanium;

forming a high-k gate insulator adjacent to said channel region;

forming a gate electrode adjacent said gate insulator, wherein said gate electrode of said first transistor and said gate electrode of said second transistor have the same mid-gap work function; and

forming a source region and a drain region on opposite sides of said gate electrode.

18. The method of claim 17, wherein said non-planar semiconductor body has a top surface and a pair of opposite sidewalls.

19. The method of claim 17, wherein said first transistor is a pMOS device and said second transistor is an nMOS device.

20. The method of claim 18, wherein forming said channel region of said first transistor comprises forming a silicon-germanium region adjacent to said top surface and adjacent to said pair of opposite sidewalls.