METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FLOATING GATE AND RELATED DEVICE
First Claim
1. A method of fabricating a semiconductor device, comprising:
- forming an isolation layer to define a fin body in a semiconductor substrate, the fin body including a first sidewall, a second sidewall opposite the first sidewall, a top surface, and a portion protruding above the isolation layer;
forming a sacrificial pattern on the isolation layer, the sacrificial pattern including an opening self-aligned with the protruding portion of the fin body and exposing the protruding portion of the fin body;
forming an insulated floating gate pattern to at least partially fill the opening;
removing the sacrificial pattern;
forming an inter-gate dielectric layer over the floating gate pattern;
forming a control gate conductive layer over the inter-gate dielectric layer; and
patterning the control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern to form a control gate electrode crossing the fin body and a floating gate electrode interposed between the control gate electrode and the fin body.
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Accused Products
Abstract
A semiconductor device such as a flash memory device having a self-aligned floating gate and a method of fabricating the same is provided. An embodiment of the device includes an isolation layer defining a fin body is formed in a semiconductor substrate. The fin body has a portion protruding above the isolation layer. A sacrificial pattern is formed on the isolation layer. The sacrificial pattern has an opening self-aligned with the protruding portion of the fin body. The protruding fin body is exposed in the opening. An insulated floating gate pattern is formed to fill the opening. The sacrificial pattern is then removed. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed over the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are patterned to form a control gate electrode crossing the fin body as well as the insulated floating gate interposed between the control gate electrode and the fin body.
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Citations
27 Claims
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1. A method of fabricating a semiconductor device, comprising:
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forming an isolation layer to define a fin body in a semiconductor substrate, the fin body including a first sidewall, a second sidewall opposite the first sidewall, a top surface, and a portion protruding above the isolation layer;
forming a sacrificial pattern on the isolation layer, the sacrificial pattern including an opening self-aligned with the protruding portion of the fin body and exposing the protruding portion of the fin body;
forming an insulated floating gate pattern to at least partially fill the opening;
removing the sacrificial pattern;
forming an inter-gate dielectric layer over the floating gate pattern;
forming a control gate conductive layer over the inter-gate dielectric layer; and
patterning the control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern to form a control gate electrode crossing the fin body and a floating gate electrode interposed between the control gate electrode and the fin body. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of fabricating a semiconductor device, comprising:
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forming an isolation layer in a semiconductor substrate to define a fin body, the fin body protruding above the isolation layer and including a first sidewall, a second sidewall, and a top surface;
forming a sacrificial spacer to cover the first and second sidewall of the fin body and at least a portion of the isolation layer;
forming a sacrificial layer over the sacrificial spacer and the isolation layer;
etching the sacrificial spacer, a portion of the sacrificial layer, and a portion of the isolation layer to form a sacrificial pattern including an opening self-aligned with the fin body;
forming an insulated floating gate pattern in the self-aligned opening to cover the exposed portions of the first and second sidewalls of the fin body and the top surface of the fin body;
removing the sacrificial pattern and etching another portion of the isolation layer such that an upper surface of the etched isolation layer not adjoining the floating gate pattern is lower than a lower end of the floating gate pattern;
forming an inter-gate dielectric layer to cover the floating gate pattern;
forming a control gate conductive layer to cover the inter-gate dielectric layer; and
patterning the control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern to form a control gate electrode crossing the fin body and a floating gate electrode interposed between the control gate electrode and the fin body. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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24. A semiconductor device comprising:
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an isolation layer defining a fin body in a semiconductor substrate, the fin body including a first sidewall, a second sidewall opposite the first sidewall, a top surface, and a portion protruding above the isolation layer;
an insulated control gate electrode crossing the fin body; and
an insulated floating gate disposed between the control gate electrode and the fin body, the floating gate covering the first sidewall, the second sidewall, and the top surface of the protruding fin body, wherein the floating gate is self-aligned with the protruding portion of the fin body. - View Dependent Claims (25, 26, 27)
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Specification