Power core devices and methods of making thereof

• US 20070090511A1
• Filed: 08/31/2006
• Published: 04/26/2007
• Est. Priority Date: 10/21/2005
• Status: Active Grant

• Current Assignee: Chemtron Research LLC (Intellectual Ventures LLC)
• Original Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.)
• Inventors: Borland, William, Ferguson, Saul
• Granted Patent: US 7,701,052 B2
• Time in Patent Office: Days
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09763 Printed component having superposed conductors, but integrated in one circuit layer
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array

Abstract

A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively.

Claims

1. A device comprising a power core wherein said power core comprises:

at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively.

2. The device of claim 1 wherein said semiconductor device is a microprocessor.

3. The device of claim 1 where the at least one singulated embedded capacitor is connected in parallel to at least one planar capacitor laminate wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said embedded singulated capacitor.

4. The device of claim 1 wherein said power core is interconnected to at least one signal layer.

8. The device of any one of claims 1 through 4 wherein additional passive components are connected to and external to said power core.

5. A method for making a device comprising:

providing at least one planar capacitor having a patterned side and a non-patterned side;

providing at least one foil structure comprising at least one formed-on-foil singulated capacitor having a foil side and a component side; and

laminating said foil side of said formed-on-foil structure to said patterned side of said planar capacitor structure etching said foil side of said formed-on-foil structure and etching said non-patterned side of said planar capacitor structure forming a power core; and

forming at least one signal layer as part of said power core.

6. The method of claim 5 wherein said signal layer is formed by applying a dielectric layer to the planar capacitor surface of said power core;

forming circuitry comprising one or more signal lines on said dielectric layer; and

forming a conductive interconnection between layers comprising said signal lines.

7. The method of claim 6 wherein said interconnection between layers is a conductive via.