Information device

• US 20070091122A1
• Filed: 10/23/2006
• Published: 04/26/2007
• Est. Priority Date: 10/26/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Koyama, Masayuki, Arakawa, Takahiko, Ando, Tomoko, Nagano, Hideo, Hatakenaka, Makoto, Muramatsu, Kikuo, Higashida, Motoki
• Granted Patent: US 7,716,410 B2
• Time in Patent Office: Days
• US Class Current: 345/629
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/775 between a recording apparatus and a television receiver
• CPC Class Codes: H04N 5/85 on discs or drums

Abstract

An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.

Claims

1. An information device comprising:

a main processing circuit for executing signal processing related to a main function in said information device;

a first microcomputer for controlling said main processing circuit;

an interface circuit for interfacing with the outside of said information device; and

a second microcomputer for controlling said interface circuit, said second microcomputer being provided separately from said first microcomputer.

2. The information device according to claim 1, wherein

said interface circuit and said second microcomputer are subjected to a single-chip process separately from said main processing circuit and said first microcomputer.

3. The information device according to claim 1, wherein

said interface circuit and said second microcomputer are connected to each other by using a parallel interface.

4. The information device according to claim 2, further comprising

a memory for storing firmware for controlling said interface circuit, said memory being formed on a semiconductor chip different from another semiconductor chip on which said second microcomputer is formed,

wherein said second microcomputer downloads said firmware from said memory to execute said firmware.

5. The information device according to claim 2, wherein

said interface circuit receives an externally inputted video signal and an externally inputted audio signal corresponding to said video signal to output said video signal and said audio signal in parallel,

said information device further comprising

a lip-sync circuit for adjusting the timing between said video signal and said audio signal outputted in parallel from said interface circuit, said lip-sync circuit being subjected to the single-chip process together with said interface circuit and said second microcomputer.

6. The information device according to claim 2, wherein

said interface circuit includes

a receiver circuit for receiving an external signal to output said external signal, and

a transmitter circuit for outputting a signal outputted from said receiver circuit to the outside of said information device.

7. The information device according to claim 2, wherein said second microcomputer has the function of communicating with said first microcomputer.

8. The information device according to claim 2, wherein

said interface circuit includes first and second interface circuits for interfacing with the outside of said information device under different specifications,

said information device further comprising

a selection circuit for activating one of said first and second interface circuits in accordance with the specification of an external signal, said selection circuit being subjected to the single-chip process together with said interface circuit and said second microcomputer.

9. The information device according to claim 2, further comprising:

a plurality of input ports for receiving respective external signals; and

a switch circuit for selecting one of the external signals inputted to said plurality of input ports to output a selected signal to said interface circuit, said switch circuit being subjected to the single-chip process together with said interface circuit and said second microcomputer.

10. The information device according to claim 2, wherein

said interface circuit receives an encrypted signal inputted from the outside of said information device, decrypts said encrypted signal, and outputs the decrypted signal,

said information device further comprising

a watermarking circuit for embedding a watermark into a signal outputted from said interface circuit to output the resultant signal, said watermarking circuit being subjected to the single-chip process together with said interface circuit and said second microcomputer.

11. The information device according to claim 1, wherein

said interface circuit is an interface circuit conforming to HDMI (High-Definition Multimedia Interface).