Electrostatic discharge protection structure and thin film transistor substrate including the same

• US 20070091218A1
• Filed: 10/25/2005
• Published: 04/26/2007
• Est. Priority Date: 10/25/2005
• Status: Abandoned Application

• Current Assignee: Chunghwa Picture Tubes Limited (Tatung Co., Ltd.)
• Original Assignee: Chunghwa Picture Tubes Limited (Tatung Co., Ltd.)
• Inventors: Huang, Chin-Hai, Shiau, Fu-Yuan, Yu, Hong-Tian
• Application Number:
  US11/163,605
• Publication Number:
  US 20070091218A1
• Time in Patent Office: Days
• US Class Current: 349/40
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures

Abstract

An electrostatic discharge protection structure contains a short ring surrounding a display region comprising pixel electrodes and thin film transistors, a plurality of switching elements disposed between the display region and the short ring corresponding to the scan lines and data lines, at least one of which is turned on to electrically connect the short ring and the scan lines and the data lines for introducing electrostatic charges to the short ring when a specific amount of electrostatic charges accumulate on the scan lines and the data lines, a conducting wire electrically connecting a storage capacitor line and the short ring, and a floating conductive pattern crossing over and not contacting the conducting wire, thereby assisting the electrostatic charges in distributing in the floating conductive pattern. Thus, an electrostatic discharge protection can be performed efficiently without increasing the substrate size.

Claims

1. An electrostatic discharge protection structure positioned on a thin film transistor substrate including a transparent insulating substrate, a plurality of scan lines, a plurality of data lines, a plurality of storage capacitor lines, a plurality of thin film transistors, and a plurality of pixel electrodes on pixel regions defined by the scan lines and the data lines, comprising:

a short ring formed on the transparent insulating substrate for surrounding a display region comprising the pixel electrodes and the thin film transistors;

a plurality of switching elements disposed between the display region and the short ring corresponding to the scan lines and the data lines, at least one of which is turned on to electrically connect the short ring and the scan lines and the data lines for introducing electrostatic charges to the short ring when a specific amount of electrostatic charges accumulate on the scan lines and the data lines;

a conducting wire electrically connecting one of the storage capacitor lines and the short ring; and

a floating conductive pattern crossing over and not contacting the conducting wire, thereby assisting the electrostatic charges in distributing in the floating conductive pattern.

2. The electrostatic discharge protection structure of claim 1, wherein the transparent insulating substrate comprises the display region and a non-display region, and the floating conductive pattern crosses over the conducting wire in the non-display region.

3. The electrostatic discharge protection structure of claim 1, wherein the transparent insulating substrate comprises the display region and a non-display region, and the floating conductive pattern crosses over the conducting wire in an outer lead bonding region of the non-display region.

4. The electrostatic discharge protection structure of claim 3, wherein a plurality of source driver IC chips and a plurality of gate driver IC chips are positioned in the outer lead bonding region for outputting image data signals to the data lines and outputting switch/addressing signals to the scan lines, respectively.

5. The electrostatic discharge protection structure of claim 1, wherein the transparent insulating substrate comprises the display region and a non-display region, and the conducting wire is electrically connected to one of the storage capacitor lines positioned in the non-display region.

6. The electrostatic discharge protection structure of claim 1, wherein the conducting wire is formed to have the same material as that of the scan lines and is formed simultaneously with the scan lines, and the floating conductive pattern is formed to have the same material as that of the data lines and is formed simultaneously with the data lines.

7. The electrostatic discharge protection structure of claim 1, wherein the conducting wire is formed to have the same material as that of the data lines and is formed simultaneously with the data lines, and the floating conductive pattern is formed to have the same material as that of the scan lines and is formed simultaneously with the scan lines.

8. The electrostatic discharge protection structure of claim 1, further comprising:

an outer short ring formed on the transparent insulating substrate for surrounding the short ring; and

a plurality of switching elements disposed between the short ring and the outer short ring to be turned on for electrically connecting the outer short ring and the short ring to introduce electrostatic charges into the outer short ring when a specific amount of electrostatic charges on the short ring has accumulated.

9. A thin film transistor substrate, comprising:

a transparent insulating substrate;

a plurality of scan lines formed on the transparent insulating substrate,

a plurality of scan lines formed on the transparent insulating substrate and intersecting the scan lines respectively;

a plurality of thin film transistors formed on the transparent insulating substrate, wherein, each thin film transistor comprises a gate, a channel, a source, and a drain, and the gates are electrically connected to the scan lines and the source are electrically connected to the data lines;

a plurality of pixel electrodes formed in a plurality of pixel regions defined by the scan lines and the data lines;

a plurality of storage capacitor lines formed on the transparent insulating substrate such that a plurality of storage capacitors are formed with the storage capacitor lines and the pixel electrodes with an insulating layer therebetween;

a short ring formed on the transparent insulating substrate for surrounding a display region comprising the pixel electrodes and the thin film transistors;

a plurality of switching elements disposed between the display region and the short ring corresponding to the scan lines and data lines, at least one of which is turned on to electrically connect the short ring and the scan lines and the data lines for introducing electrostatic charges to the short ring when a specific amount of electrostatic charges accumulate on the scan lines and the data lines;

a conducting wire electrically connecting one of the storage capacitor lines and the short ring; and

a floating conductive pattern crossing over and not contacting the conducting wire, thereby assisting the electrostatic charges in distributing in the floating conductive pattern.

10. The thin film transistor substrate of claim 9, wherein the transparent insulating substrate comprises the display region and a non-display region, and the non-display region comprises an outer lead bonding region.

11. The thin film transistor substrate of claim 10, wherein the floating conductive pattern crosses over the conducting wire at the outer lead bonding region.

12. The thin film transistor substrate of claim 10, wherein the conducting wire is electrically connected to one of the storage capacitor lines positioned in the non-display region.

13. The thin film transistor substrate of claim 10, further comprises a plurality of source driver IC chips and a plurality of gate driver IC chips on the outer lead bonding region for outputting image data signals to the data lines and outputting switch/addressing signals to the scan lines, respectively.

14. The thin film transistor substrate of claim 9, wherein the conducting wire is formed to have the same material as that of the scan lines and is formed simultaneously with the scan lines, and the floating conductive pattern is formed to have the same material as that of the data lines and is formed simultaneously with the data lines.

15. The thin film transistor substrate of claim 9, wherein the conducting wire is formed to have the same material as that of the data lines and is formed simultaneously with the data lines, and the floating conductive pattern is formed to have the same material as that of the scan lines and is formed simultaneously with the scan lines.

16. The thin film transistor substrate of claim 10, further comprising:

an outer short ring formed on the transparent insulating substrate for surrounding the short ring; and

a plurality of switching elements disposed between the short ring and the outer short ring to be turned on for electrically connecting the outer short ring and the short ring to introduce electrostatic charges into the outer short ring when a specific amount of electrostatic charges on the short ring has accumulated.