Method for recovering from errors in flash memory

• US 20070091677A1
• Filed: 04/05/2006
• Published: 04/26/2007
• Est. Priority Date: 10/25/2005
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Lasser, Menahem, Murin, Mark
• Granted Patent: US 7,954,037 B2
• Time in Patent Office: Days
• US Class Current: 365/185.09
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

Methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors are disclosed. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, for example, until a successful error correction may be carried out. In some embodiments, after successful error correction a subsequent read request is handled without re-writing data (for example, reliable values of the read data) to the flash memory cells in the interim. In some embodiments, reference voltages associated with a reading where errors are corrected may be stored in memory, and retrieved when responding to a subsequent read request. In some embodiments, the modified reference voltages are predetermined reference voltages. Alternatively or additionally, these modified reference voltages may be determined as needed, for example, using randomly generated values or in accordance with information provided by the error detection and correction module. Methods, devices and computer readable code for reading data for situations where there is no error correction failure are also provided.

Claims

1. ) In a system comprising a plurality of flash memory cells and an error detection and correction module, a method of reading data, the method comprising:

a) reading data bits from the plurality of flash memory cells;

b) attempting to correct errors of said read data bits using the error detection and correction module;

c) in the event of an error correction failure by the error detection and correction module, re-reading, at least once, said data bits from the plurality of flash memory cells using at least one modified reference voltage until the module successfully corrects said errors; and

d) repeating steps (a), (b) and (c) for said data bits without re-writing said data bits to the memory cells in the interim.

2. ) The method of claim 1 wherein an initial said reading before said repeating is in response to a first read request, and a subsequent reading associated with said repeating is in response to a subsequent read request.

3. ) In a system comprising a plurality of flash memory cells and an error detection and correction module, a method of reading data, the method comprising:

a) reading data bits from the plurality of flash memory cells;

b) attempting to correct errors of said read data bits using the error detection and correction module;

c) in the event of an error correction failure by the error detection and correction module, re-reading, at least once, said data bits from the plurality of flash memory cells using at least one modified reference voltage until the module successfully corrects said errors;

d) subsequent to said correcting, storing at least one read reference voltage for which the module successfully corrected said errors;

e) subsequent to said storing, retrieving said stored at least one read reference voltage; and

g) subsequent to said retrieving, reading the data bits from the plurality of flash memory cells using said retrieved at least one read reference voltage.

4. ) The method of claim 3 wherein at least one said read reference voltage is stored in volatile memory.

5. ) The method of claim 3 wherein at least one said read reference voltage is stored in non-volatile memory.

6. ) The method of claim 3 wherein at least one said read reference voltage is stored in one or more of the flash memory cells.

7. ) The method of claim 3 wherein said read data bits are read using a flash controller, and at least one said read reference voltage is stored in said flash controller.

8. ) The method of claim 3 wherein an initial said reading before said storing is in response to a first read request, and a subsequent reading using said retrieved at least one read reference voltage is in response to a subsequent read request.

9. ) In a system comprising a plurality of flash memory cells and an error detection and correction module, a method of reading data, the method comprising:

a) reading data bits from the plurality of flash memory cells;

b) attempting to correct errors of said read data bits using the error detection and correction module;

c) in the event of an error correction failure by the error detection and correction module and subsequent to said reading, deriving at least one new read reference voltage; and

d) reading said data bits from the plurality of flash memory cells using said derived at least one new read reference voltage.

10. ) The method of claim 9 wherein said derived at least one new voltage is determined at least in part in accordance with information provided by the error detection and correction module.

11. ) The method of claim 9 wherein said derived at least one new voltage is determined at least in part randomly.

12. ) In a system comprising a plurality of flash memory cells and an error detection and correction module, a method of reading data, the method comprising:

a) reading data bits from the plurality of flash memory cells;

b) correcting errors of said read data bits using the error detection and correction module; and

c) subsequent to said correcting, reading said data bits from the plurality of flash memory cells using at least one modified reference voltage.

13. ) The method of claim 12 wherein the plurality of memory cells are not written after said correcting and before said reading using said at least one modified reference voltage.

14. ) The method of claim 12 wherein at least one said modified reference voltage is derived in accordance at least in part with information provided by the error detection and correction module.

15. ) The method of claim 12. wherein an initial said reading before said correcting is in response to a first read request, and said subsequent reading after said correcting is in response to a subsequent read request.

16. ) A flash memory device for data storage, the device comprising:

a) a plurality of flash memory cells for storing data bits;

b) an error detection and correction module for detecting and correcting errors in said data bits; and

c) a controller for reading said data bits from said memory cells, wherein;

i) said controller is operative to respond to a first read request by reading data bits from said plurality of flash memory cells and, if said error detection and correction module fails to correct said data bits, re-read the data bits using at least one modified reference voltage until said module successfully corrects said errors; and

ii) said controller is further operative to repeat said response for a subsequent read request without re-writing said data bits to the memory cells in the interim.

17. ) A flash memory device for data storage, the device comprising:

a) a plurality of flash memory cells for storing data bits;

b) an error detection and correction module for detecting and correcting errors in said data bits; and

c) a controller for reading said data bits from said flash memory cells, wherein said controller is operative to respond to a first read request by;

i) reading data bits from the plurality of flash memory cells;

ii) attempting to correct errors of said read data bits using said error detection and correction module;

iii) in the event of an error correction failure by the error detection and correction module, re-reading, at least once, the data bits from said plurality of flash memory cells using at least one modified reference voltage until said module successfully corrects said errors; and

iv) subsequent to said correcting, storing, at least one read reference voltage for which the module successfully corrected said errors;

and, subsequent to said storing, said controller is further operative to respond to a subsequent read request by;

i) retrieving said stored at least one read reference voltage; and

ii) subsequent to said retrieving, reading the data bits from the plurality of flash memory cells using said retrieved at least one read reference voltage.

18. ) The device of claim 17 wherein said controller is operative to store at least one said read reference voltage in volatile memory.

19. ) The device of claim 17 wherein said controller is operative to store at least one said read reference voltage in non-volatile memory.

20. ) The device of claim 17 wherein said controller is operative to store at least one said read reference voltage in one or more said flash memory cells.

21. ) The device of claim 17 wherein said controller is operative to store at least one said read reference voltage in said controller.

22. ) A flash memory device for data storage, the device comprising:

a) a plurality of flash memory cells for storing data bits;

b) an error detection and correction module for detecting errors in said data bits; and

c) a controller for reading said data bits from said flash memory cells, wherein said controller is operative to respond to a read request by;

i) reading said data bits from the plurality of flash memory cells;

ii) attempting to correct errors of said read data bits using the error detection and correction module;

iii) in the event of an error correction failure by the error detection and correction module and subsequent to said reading, deriving at least one new read reference voltage, and

iv) reading said data bits from the plurality of flash memory cells using said derived at least one new read reference voltage.

23. ) The device of claim 22 wherein said controller is operative to derive said at least one new voltage at least in part in accordance with information provided by the error detection and correction module.

24. ) The device of claim 22 wherein said controller is operative to derive said at least one new voltage at least in part randomly.

25. ) A flash memory device for data storage, the device comprising:

a) a plurality of flash memory cells for storing data bits;

b) an error detection and correction module for detecting errors in said data bits; and

c) a controller for reading said data bits from said flash memory cells, wherein said controller is operative to respond to a first read request by;

i) reading data bits from the plurality of flash memory cells; and

ii) correcting errors of said read data bits, using said error detection and correction module,

and said controller is operative to respond to a subsequent read request by;

iii) reading the data bits from the plurality of flash memory cells using at least one modified reference voltage.

26. ) The device of claim 25 wherein said controller is operative to respond to said first and said subsequent read requests without writing to said plurality of memory cells after said correcting and before said reading using said at least one modified reference voltage.

27. ) The device of claim 25 wherein said controller is operative to derive at least one said modified reference voltage in accordance at least in part with information provided by said error detection and correction module.

28. ) A computer readable storage medium having computer readable code embodied in said computer readable storage medium, said computer readable code comprising instructions for reading data in a system comprising a plurality of flash memory cells and an error detection and correction module, wherein said instructions comprise instructions to:

a) read data bits from said plurality of flash memory cells;

b) attempt to correct errors of said read data bits using said error detection and correction module;

c) in the event of an error correction failure by the error detection and correction module, re-read, at least once, said data bits from the plurality of flash memory cells using at least one modified reference voltage until the module successfully corrects said errors; and

d) repeat steps (a), (b) and (c) without writing re-writing said data bits to the memory cells in the interim.

29. ) A computer readable storage medium having computer readable code embodied in said computer readable storage medium, said computer readable code comprising instructions for reading data in a system comprising a plurality of flash memory cells and an error detection and correction module, wherein said instructions comprise instructions to:

a) read data bits from the plurality of flash memory cells;

b) attempt to correct errors of said read data bits using the error detection and correction module;

c) in the event of an error correction failure by the error detection and correction module, re-read, at least once, said data bits from the plurality of flash memory cells using at least one modified reference voltage until the module successfully corrects said errors;

d) subsequent to said correcting, store at least one read reference voltage for which the module successfully corrected said errors;

e) subsequent to said storing, retrieve said stored at least one read reference voltage; and

g) subsequent to said retrieving, read the data bits from the plurality of flash memory cells using said retrieved at least one read reference voltage.

30. ) A computer readable storage medium having computer readable code embodied in said computer readable storage medium, said computer readable code comprising instructions for reading data in a system comprising a plurality of flash memory cells and an error detection and correction module, wherein said instructions comprise instructions to:

a) read data bits from the plurality of flash memory cells;

b) attempt to correct errors of said read data bits using the error detection and correction module;

c) in the event of an error correction failure by the error detection and correction module and subsequent to said reading, derive at least one new read reference voltage; and

d) read said data bits from the plurality of flash memory cells using said derived at least one new read reference voltage.

31. ) A computer readable storage medium having computer readable code embodied in said computer readable storage medium, said computer readable code comprising instructions for reading data in a system comprising a plurality of flash memory cells and an error detection and correction module, wherein said instructions comprise instructions to:

a) read data bits from the plurality of flash memory cells;

b) correct errors of said read data bits using the error detection and correction module; and

c) subsequent to said correcting, read said data bits from the plurality of flash memory cells using at least one modified reference voltage.