High-speed adaptive interconnect architecture with nonlinear error functions
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Abstract
A low cost and high speed equalizing receiver structure is provided for improved inter-chip and inter-module communications. The receiver is able to recover data from a corrupted waveform from a signal wire such as one found on data, address or control wires in a microsystem architecture. The receiver can be used with binary as well as m-ary pulse amplitude modulation schemes. The receiver can be used to increase the sustainable data rate between chips or can be used to sustain a given data rate over a poorer quality channel as compared to prior art interconnect technologies. Methods for training and operating the receiver structure are provided. A novel structure called the decision feedback equalizer and cross talk canceller (DFE-CTC) is introduced and methods to compute the coefficients to minimize error in terms of the l2 norm, the l∞ norm, and statistical probability of error functions are also disclosed.
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Citations
35 Claims
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1-20. -20. (canceled)
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21. A system comprising:
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a first electronic subsystem formed on a first semiconductor substrate;
a second electronic subsystem formed on a second semiconductor substrate;
a third substrate onto which is mounted the first electronic subsystem, the second electronic subsystem, and an inter-chip high-speed bus wire trace, wherein the inter-chip high-speed bus wire trace electrically couples an output pad of the first semiconductor substrate to an input pad of the second semiconductor substrate;
a 1-bit sampling circuit coupled to the input pad and operative to convert an analog signal received on the input pad to a stream of 1-bit digital sample values wherein the 1-bit sampling circuit produces its stream of 1-bit digital sample values at a specified sampling rate; and
an equalizer that processes the stream of 1-bit digital sample values using a feed forward filter channel that includes a multiplier free adder-based circuit that combines a set of equalizer coefficients with one or more of the 1-bit digital sample values to produce a recovered signal sequence, wherein the recovered signal sequence has a reduced sample rate that is at least two times less than the specified sampling rate, wherein the equalizer is characterized in that its coefficients are selected to reduce a measure of a residual error signal. - View Dependent Claims (22, 23, 24)
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24-1. The system of claim 21, wherein the 1-bit sampling circuit comprises a sigma-delta quantizer.
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25. A system comprising:
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a first electronic subsystem formed on a first semiconductor substrate;
a second electronic subsystem formed on a second semiconductor substrate;
a third substrate onto which is mounted the first electronic subsystem, the second electronic subsystem, a first inter-chip high-speed bus wire trace that electrically couples a first output pad of the first semiconductor substrate to a first input pad of a second semiconductor substrate, and a set of one or more second high-speed bus wire traces that are collocated on the third substrate and that electrically couple one or more second output pads of the first semiconductor substrate to one or more second output pads of the second semiconductor substrate;
wherein the second electronic subsystem further comprises;
a plurality of 1-bit sampling circuits, wherein at least one of the 1-bit sampling circuits is coupled to the first input pad and others of the 1-bit sampling circuits are coupled to respective ones of the set of one or more second input pads, wherein each 1-bit sampling circuit is operative to convert an analog signal received on its respective input pad to a respective stream of 1-bit digital sample values, wherein each said sampling circuit produces its respective stream of 1-bit digital sample values at a first sampling rate;
a plurality of feed-forward filter channels that each linearly combine a respective stream of 1-bit digital sample values using a respective multiplier free adder-based circuit to produce a respective output sequence, wherein each said output sequence has a second sampling rate that is at least two times less than the first sampling rate; and
a linear combining circuit coupled to the outputs of each of the plurality of feed-forward filter channels, the linear combining circuit operative to linearly combine the outputs of each of the plurality of feed-forward filter channels. - View Dependent Claims (26, 27)
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28. An equalizer that processes a communication signal, the equalizer comprising:
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a sigma-delta quantizer operative to convert an input analog signal representative of a received version of the communication signal to a stream of sigma-delta quantized sample values, wherein the sigma-delta quantizer produces the stream of sigma-delta quantized sample values at a specified sampling rate;
a feed forward filter that processes the stream of sigma-delta quantized sample values using an adder-based circuit that logically combines a set of equalizer coefficients of a coefficient vector with one or more of the sigma-delta quantized sample values so as to produce a recovered signal sequence, wherein the recovered signal sequence has a reduced sample rate that is at least two times less than the specified sampling rate, and the coefficient vector is selected to reduce a measure of error in the recovered signal sequence. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35)
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Specification