Method of making an inverted-T channel transistor

• US 20070093010A1
• Filed: 10/25/2005
• Published: 04/26/2007
• Est. Priority Date: 10/25/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mathew, Leo, Mora, Rode
• Granted Patent: US 8,513,066 B2
• Time in Patent Office: Days
• US Class Current: 438/182
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region. The method further includes removing a portion of the horizontal active region, which is not covered by the sidewall spacer. The method further includes removing the sidewall spacer. The method further includes forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region. The method further includes forming a gate electrode over the gate dielectric. The method further includes forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.

Claims

1. A method for creating an inverse T field effect transistor, comprising:

creating a horizontal active region and a vertical active region on a substrate;

forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region;

removing a portion of the horizontal active region, which is not covered by the sidewall spacer;

removing the sidewall spacer;

forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region;

forming a gate electrode over the gate dielectric; and

forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.

2. The method of claim 1 further comprising forming a liner on the horizontal active region and the vertical active region.

3. The method of claim 2, wherein the liner is used as an etch-stop layer for forming the sidewall spacer.

4. The method of claim 2, wherein the liner comprises silicon oxide.

5. The method of claim 1, wherein the sidewall spacer comprises one of silicon nitride or silicon oxide.

6. The method of claim 1 further comprising, after removing the portion of the horizontal active region, which is not covered by the sidewall spacer, oxidizing any exposed portion of the horizontal active region.

7. The method of claim 1, wherein the sidewall spacer has a base, which is substantially equal in terms of its width on each side of the vertical active region.

8. The method of claim 1, wherein removing the sidewall spacer comprises using a wet-etch process.

9. The method of claim 8, wherein phosphoric acid is used as part of the wet-etch process.

10. The method of claim 1, wherein a base width of the sidewall spacer is in a range from 10 Angstroms to 1000 Angstroms.

11. The method of claim 1, wherein a height of the horizontal active region is smaller than a width of the vertical active region.

12. A method for creating horizontal and vertical active regions on a substrate, comprising:

creating a horizontal active region and a vertical active region on the substrate;

forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region;

masking, using a mask, a portion of the horizontal active region, a portion of the vertical active region, and a portion of the sidewall spacer;

removing a portion of the sidewall spacer that is not covered by the mask; and

removing a portion of the horizontal active region, which is not covered by the sidewall spacer or the mask.

13. The method of claim 12 further comprising forming a liner on the horizontal active region and the vertical active region.

14. The method of claim 13, wherein the liner is used as an etch-stop layer for forming the sidewall spacer.

15. The method of claim 13, wherein the liner comprises silicon oxide.

16. The method of claim 12, wherein the sidewall spacer comprises one of silicon nitride or silicon oxide.

17. A method for creating a L-shaped channel for a field effect transistor, comprising:

creating a horizontal active region and a vertical active region on a substrate;

forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region;

removing the sidewall spacer from one of the first side of the vertical active region or the second side of the vertical active region;

removing a portion of the horizontal active region, which is not covered by the sidewall spacer;

removing the sidewall spacer;

forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region;

forming a gate electrode over the gate dielectric; and

forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.

18. The method of claim 17, further comprising forming a liner on the horizontal active region and the vertical active region.

19. The method of claim 18, wherein the liner is used as an etch-stop layer for forming the sidewall spacer.

20. The method of claim 18, wherein the liner comprises silicon oxide and wherein the sidewall spacer comprises one of silicon nitride or silicon oxide.

21. The method of claim 17 further comprising, after removing the portion of the horizontal active region, which is not covered by the sidewall spacer, oxidizing any exposed portion of the horizontal active region.