Split gate flash memory cell and fabrication method thereof

• US 20070093024A1
• Filed: 03/28/2006
• Published: 04/26/2007
• Est. Priority Date: 10/26/2005
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Lu, Chien-Chung, Liao, Hung-Kwei, Fu, Ching-Hung
• Granted Patent: US 7,485,917 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7886 Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS

Abstract

A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.

Claims

1. A method of fabricating a split gate flash memory cell, comprising:

providing a semiconductor substrate;

forming a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a cap layer on the semiconductor substrate in sequence;

performing a first etching process to remove a portion of the cap layer, a portion of the second conductive layer and a portion of the second insulating layer to expose a portion of the surface of the first conductive layer, wherein the etched cap layer, the etched second conductive layer and the etched second insulating layer have coplanar sidewalls;

forming a first sidewall spacer and a second sidewall spacer on the sidewalls of the etched cap layer, the etched second conductive layer and the etched second insulating layer, respectively;

performing a second etching, with the first sidewall spacer and the second sidewall spacer as a mask, to remove a portion of the first conductive layer and a portion of the first insulating layer, and thus, a portion of a surface of the semiconductor substrate is exposed, wherein the etched first conductive layer and the etched first insulating layer have coplanar sidewalls;

striping the first sidewall spacer and the second sidewall spacer;

forming a third insulating layer on the semiconductor substrate and the sidewalls of the etched first conductive layer and the etched first insulating layer; and

forming a third conductive layer on the third insulating layer.

2. The method as claimed in claim 1, wherein the first sidewall spacer and the second sidewall spacer comprise silicon nitride.

3. The method as claimed in claim 1, wherein the third insulating layer comprises silicon oxide.

4. The method as claimed in claim 1, wherein forming the third insulating layer comprises performing chemical vapor deposition.

5. The method as claimed in claim 1, wherein the first conductive layer, the second conductive layer and the third conductive layer comprise polysilicon.

6. The method as claimed in claim 1, wherein the second insulating layer comprises an oxide-nitride-oxide stack.

7. The method as claimed in claim 1, wherein forming the third insulating layer comprises performing thermal oxidation.

8. A split gate flash memory cell, comprising:

a semiconductor substrate;

a first insulating layer on the semiconductor substrate;

a floating gate on the first insulating layer, wherein the floating gate has a first width;

a second insulating layer on the floating gate;

a control gate on the second insulating layer;

a cap layer on the control gate, wherein the cap layer, the control gate and the second insulating layer have a same second width less than the first width;

a third insulating layer conformally disposed on sidewalls of the cap layer, the control gate, the second insulating layer, and the floating gate; and

an erase gate on the third insulating layer.

9. The split gate flash memory cell as claimed in claim 8, wherein the floating gate and the first insulating layer have the same first width.

10. The split gate flash memory cell as claimed in claim 8, wherein the cap layer comprises silicon nitride.

11. The split gate flash memory cell as claimed in claim 8, wherein the difference between the first width and the second width ranges from 50 to 400 angstroms.

12. The split gate flash memory cell as claimed in claim 8, wherein the floating gate, the control gate and the erase gate comprise polysilicon.

13. The split gate flash memory cell as claimed in claim 8, wherein the third insulating layer comprises silicon oxide.

14. The split gate flash memory cell as claimed in claim 8, wherein the second insulating layer comprises an oxide-nitride-oxide stack.

15. A method of fabricating a split gate flash memory cell, comprising:

forming a first conductive layer on a substrate;

forming a first insulating layer on the first conductive layer;

forming a second conductive layer on the first insulating layer;

forming a patterned cap layer on the second conductive layer;

using the cap layer as a mask to remove a portion of the second conductive layer and a portion of the first insulating layer, and thus, a portion of the surface of the first conductive layer is exposed;

forming a sidewall spacer on sidewalls of the remaining second conductive layer and the remaining first insulating layer;

using the sidewall spacer and the cap layer as a mask to remove a portion of the first conductive layer, and thus, a portion of a surface of the substrate is exposed;

removing the sidewall spacer;

conformally forming a second insulating layer on sidewalls of the remaining second conductive layer, the remaining first insulating layer and the remaining first conductive layer; and

forming a third conductive layer on the second insulating layer.

16. The method as claimed in claim 15, further comprising:

treating the second insulating with a thermal oxidation process.

17. The method as claimed in claim 15, wherein the sidewall spacer comprises silicon nitride.

18. The method as claimed in claim 15, wherein the second insulating layer comprises silicon oxide.

19. The method as claimed in claim 15, wherein the first conductive layer, the second conductive layer and the third conductive layer comprise polysilicon.

20. The method as claimed in claim 15, wherein the first insulating layer comprises an oxide-nitride-oxide stack.