Method and system for hardware efficient systematic approximation of square functions for communication systems

• US 20070094318A1
• Filed: 10/24/2005
• Published: 04/26/2007
• Est. Priority Date: 10/24/2005
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Lutkemeyer, Christian
• Application Number:
  US11/257,326
• Publication Number:
  US 20070094318A1
• Time in Patent Office: Days
• US Class Current: 708/290
• CPC Class Codes: G06F 2207/5523 Calculates a power, e.g. the square, of a number or a function, e.g. polynomials
• CPC Class Codes: G06F 7/552 Powers or roots , e.g. Pythagorean sums

Abstract

Certain aspects of a method and system for implementing approximation of a square function may comprise generating an output value by subtracting an absolute value of a first received input and a second received input. The generated output may be left shifted so as to generate a left shifted value. An output may be generated by left shifting by a plurality of bits, a sum of the generated left shifted value and the absolute value of the first received input. The second received input S may be determined by S=2^└log2X┘, where X is the first received input. The plurality of bits used for left shifting during generation of the output may be determined by log₂(S). A leading ‘1’ in the first received input may be detected in order to generate the second received input.

Claims

1. A method for implementing an approximation function, the method comprising:

generating a logical output value from an absolute value of a first received input and a value of a second received input;

left shifting said generated logical output value to generate a left shifted value; and

generating an output by left shifting by a plurality of bits, a sum of the following;

said generated left shifted value and said absolute value of said first received input.

2. The method according to claim 1, wherein said second received input denoted as S, is determined by S=2^└

log^2X┘

, where X is said first received input.

3. The method according to claim 1, wherein said plurality of bits is determined by log₂(S), where S is said second received input and S is determined by S=2^└

log^2X┘

, where X is said first received input.

4. The method according to claim 1, further comprising detecting a leading ‘

1’

as a most significant bit in said first received input in order to generate said second received input.

5. The method according to claim 1, further comprising generating said output by (3|X|−

2S)*S, where |X| is said absolute value of said first received input and S is said second received input and S is determined by S=2<sup>└

log2X┘</sup>

, where X is said first received input.

6. The method according to claim 1, further comprising determining Euclidean distances in Viterbi branch metric calculations utilizing said generated output.

7. The method according to claim 1, further comprising determining Euclidean distances in image classification utilizing said generated output.

8. The method according to claim 1, wherein said logical output value is generated by at least one of the following:

logical ANDing, adding and subtracting, said absolute value of said first received input and said value of said second received input.

9. The method according to claim 1, wherein said value of said second received input is a negated value of said second received input.

10. A machine-readable storage having stored thereon, a computer program having at least one code section for implementing an approximation function in a communication system, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

generating a logical output value from an absolute value of a first received input and a value of a second received input;

left shifting said generated logical output value to generate a left shifted value; and

generating an output by left shifting by a plurality of bits, a sum of the following;

said generated left shifted value and said absolute value of said first received input.

11. The machine-readable storage according to claim 10, wherein said second received input denoted as S, is determined by S=2^└

log^2X┘

, where X is said first received input.

12. The machine-readable storage according to claim 10, wherein said plurality of bits is determined by log₂(S), where S is said second received input and S is determined by S=2^└

log^2X┘

, where X is said first received input.

13. The machine-readable storage according to claim 10, further comprising code for detecting a leading ‘

1’

as a most significant bit in said first received input in order to generate said second received input.

14. The machine-readable storage according to claim 10, further comprising code for generating said output by (3|X|−

2S)*S, where |X| is said absolute value of said first received input and S is said second received input and S is determined by S=2<sup>└

log2X┘</sup>

, where X is said first received input.

15. The machine-readable storage according to claim 10, further comprising code for determining Euclidean distances in Viterbi branch metric calculations utilizing said generated output.

16. The machine-readable storage according to claim 10, further comprising code for determining Euclidean distances in image classification utilizing said generated output.

17. The machine-readable storage according to claim 10, wherein said logical output value is generated by at least one of the following:

logical ANDing, adding and subtracting, said absolute value of said first received input and said value of said second received input.

18. The machine-readable storage according to claim 10, wherein said value of said second received input is a negated value of said second received input.

19. A system for implementing a square function in a communication system, the system comprising:

circuitry that generates a logical output value from an absolute value of a first received input and a value of said second received input;

said circuitry left shifts said generated logical output value to generate a left shifted value; and

said circuitry generates an output by left shifting by a plurality of bits, a sum of the following;

said generated left shifted value and said absolute value of said first received input.

20. The system according to claim 19, wherein said second received input, denoted as S, is determined by S=2^└

log^2X┘

, where X is said first received input.

21. The system according to claim 19, wherein said plurality of bits is determined by log₂(S), where S is said second received input and S is determined by S=2^└

log^2X┘

, where X is said first received input.

22. The system according to claim 19, wherein said circuitry detects a leading ‘

1’

as a most significant bit in said first received input in order to generate said second received input.

23. The system according to claim 19, wherein said circuitry generates said output by (3|X|−

2S)*S, where |X| is said absolute value of said first received input and S is said second received input and S is determined by S=2<sup>└

log2X┘</sup>

, where X is said first received input.

24. The system according to claim 19, wherein said circuitry determines Euclidean distances in Viterbi branch metric calculations utilizing said generated output.

25. The system according to claim 19, wherein said circuitry determines Euclidean distances in image classification utilizing said generated output.

26. The system according to claim 19, wherein said logical output value is generated by at least one of the following:

logical ANDing, adding and subtracting, said absolute value of said first received input and said value of said second received input.

27. The system according to claim 19, wherein said value of said second received input is a negated value of said second received input.