Pipelined digital signal processor

• US 20070094483A1
• Filed: 10/26/2005
• Published: 04/26/2007
• Est. Priority Date: 10/26/2005
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Wilson, James, Stein, Yosef, Kablotsky, Joshua, Yukna, Gregory, Mayer, Christopher, Prendergast, Colm
• Granted Patent: US 8,024,551 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

Claims

1. A processor containing apparatus for reducing pipeline stall between compute unit and address unit comprising:

at least one compute unit for computing results in response to instructions of an algorithm;

said compute unit including a local random access memory array for storing predetermined sets of function values, related to the computed results for predetermined sets of instructions of said algorithm, to provide within the compute unit direct mapping of computed results to related function.

2. The processor of claim 1 includes a register file shared by said compute units.

3. The processor of claim 2 in which all the compute unit local random access memory arrays are filled in parallel with like values from said register file.

4. The processor of claim 2 in which local random access memory arrays are filled with different values in parallel from said register file.

5. The processor of claim 2 in which said local random access memory arrays are spilled in parallel to said register file.

6. The processor of claim 1 in which said compute circuit includes a status device indicating when one or more function values stored in a section of said random access memory array have been updated.

7. The processor of claim 6 in which said status device decides whether function values in the random access memory array should be spilled and saved.

8. The processor of claim 1 in which said mapping of the computed result to related function is independent from the previous computed result mapping.

9. The processor of claim 1 in which said mapping of the computed result to the related function is independent from one compute unit to another.

10. The processor of claim 2 in which a register from the register file may be used as an index to the random access memory arrays in multiple compute units.

11. The processor of claim 2 in which the output of the random access memory arrays in multiple compute units are combined into a single register in the register file.

12. The processor of claim 9 in which a different register from the register file is used as an index to the random access memory array in each compute unit.

13. The processor of claim 9 in which the output of each random access memory array in each compute unit is placed in different registers in the register file.

14. The processor of claim 1 in which said local random access memory array includes a look up table.

15. The processor of claim 1 further including a control unit for storing in said local random access memory array predetermined sets of said function values to provide direct mapping of computed results to related function within the compute unit.

16. The processor of claim 1 in which said compute unit includes a table base register associated with each local random access memory array for enabling related sets of data to be stored at independent addresses in each local reconfigurable fill and spill random access memory array.

17. A pipelined digital signal processor for reducing pipeline stall between compute unit and address unit comprising:

a least one compute unit for computing results in response to instructions of an algorithm;

said compute unit including a local reconfigurable fill and spill random access memory array for storing predetermined sets of values, related to the computed results for predetermined sets of instructions of said algorithm, to provide within the compute unit direct mapping of computed results to related function.

18. The pipelined digital signal processor of claim 17 includes a register file shared by said compute units.

19. The pipelined digital signal processor of claim 18 in which said register file includes an input register for filling like values in parallel across all the compute unit local reconfigurable fill and spill random access memory arrays.

20. The pipelined digital signal processor of claim 18 in which said register file includes an input register for filling different values serially in each of the compute unit local reconfigurable fill and spill random access memory arrays.

21. The pipelined digital signal processor of claim 18 in which said register file includes an output register for spilling stored values in parallel from local reconfigurable fill and spill random access memory arrays.

22. The pipelined digital signal processor of claim 18 in which said register file includes an output register for spilling stored values serially from local reconfigurable fill and spill random access memory arrays.

23. The pipelined digital signal processor of claim 17 in which said compute circuit includes a status device for enabling spilling of values from at least a section of said local reconfigurable fill and spill random access memory array when one or more of said values stored in said section have been updated.

24. The pipelined digital signal processor of claim 17 in which said mapping of the computed result to related function values is independent from the previous computed result mapping;

25. The pipelined digital signal processor of claim 18 in which said register file includes an input register shared by local reconfigurable fill and spill random access memory arrays and an output register shared by local reconfigurable fill and spill random access memory arrays.

26. The pipelined digital signal processor of claim 25 in which said input register receives a different computed result for each local reconfigurable fill and spill random access memory array and said output register presents a different function value from each local reconfigurable fill and spill random access memory array.

27. The pipelined digital signal processor of claim 25 in which said input register receives the same computed result for each local reconfigurable fill and spill random access memory array and the output register presents a single function value constituted by the function parts presented by each of the local reconfigurable fill and spill random access memory arrays.

28. The pipelined digital signal processor of claim 17 in which said local reconfigurable fill and spill random access memory array includes a look up table.

29. The pipelined digital signal processor of claim 17 further including a control unit for storing in said local reconfigurable fill and spill random access memory array predetermined sets of function values related to the computed results for predetermined sets of instructions in the algorithm, to provide direct mapping of computed results to related function within the compute unit.

30. The pipelined digital signal processor of claim 17 in which said compute unit includes a table base register associated with each local reconfigurable fill and spill random access memory array for enabling related sets of data to be stored at independent addresses in each local reconfigurable fill and spill random access memory array.

31. A method for reducing pipeline stall between a compute unit and address unit in a processor comprising:

computing results in a compute unit in response to instructions of an algorithm;

storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of said algorithm; and

providing within the compute unit direct mapping of computed results to related function.

32. The method of claim 31 in which the processor includes a register file shared by said compute units.

33. The method of claim 32 which includes filling all the compute unit local random access memory arrays in parallel with like values from said register file.

34. The method of claim 32 which includes filling local random access memory arrays with different values in parallel from said register file.

35. The method of claim 32 which includes spilling said local random access memory arrays in parallel to said register file.

36. The method of claim 31 further including indicating in a status device in said compute circuit when one or more values stored in a section of said random access memory array have been updated.

37. The method of claim 36 further including deciding in said status device whether values in the random access memory array should be spilled and saved.

38. The method of claim 31 further including mapping the computed result to related function independently from the previous computed result mapping.

39. The method of claim 31 further including mapping the computed result to the related function value independently from one compute unit to another.

40. The method of claim 32 in which a register from the register file is used as an index to the random access memory arrays in multiple compute units.

41. The method of claim 32 further including combining the output of the random access memory arrays in multiple compute units into a single register in the register file.

42. The method of claim 39 further including using a different register from the register file as an index to the random access memory array in each compute unit.

43. The method of claim 39 further including placing the output of each random access memory array in each compute unit in different registers in the register file.

44. The method of claim 31 in which said local random access memory array includes a look up table.

45. The method of claim 31 further including storing in said local random access memory array predetermined sets of instructions of said algorithm, to provide direct mapping of computed results to related function value within the compute unit.

46. The method of claim 31 in which related sets of data are stored at independent addresses in each local reconfigurable fill and spill random access memory array using a table base register associated with each local random access memory array in the compute unit.