DECODING OF MULTIPLE DATA STREAMS ENCODED USING A BLOCK CODING ALGORITHM

• US 20070094565A1
• Filed: 09/22/2006
• Published: 04/26/2007
• Est. Priority Date: 09/23/2005
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Paumier, Laurent, Urard, Pascal, Comminges, Martial
• Granted Patent: US 7,725,810 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: H03M 13/1105 Decoding
• CPC Class Codes: H03M 13/1134 Full parallel processing, i.e. all bit nodes or check nodes are processed in parallel
• CPC Class Codes: H03M 13/1137 Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/6505 Memory efficient implementations
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions

Abstract

A system implemented for example in the form of an SoC comprises a first demodulator for generating a first data stream to be decoded, and a second demodulator for generating a second data stream to be decoded, and a block decoder. The block decoder comprises an input memory for storing blocks of data from the first data stream and blocks of data from the second data stream, and a block decoding unit for processing, from the input memory, the blocks of data from the first and second data streams.

Claims

1. A block decoder, comprising:

a first input and at least a second input for respectively receiving a first data stream to be decoded and a second data stream to be decoded distinct from said first data stream;

an input memory with storage elements configured to store at least one block of data from the first data stream and at least one block of data from the second data stream;

a block decoding unit configured to process, from the input memory, the blocks of data from the first and second data streams to be decoded; and

a control unit to multiplex the blocks of data from the first data stream and the blocks of data from the second data stream as input into the block decoding unit, by saving and reading said blocks in the storage elements of the input memory, wherein

a sum of the respective maximum bit rates for each of the first and second data streams is less than M, where M indicates a maximum input bit rate for the block decoding unit; and

the input memory includes at least four storage elements, each configured to store a block of data to be decoded, and used by order of priority or in a circular manner to store the data to be decoded from the first data stream and the data to be decoded from the second data stream.

2. A block decoder according to claim 1 wherein at least three flags are associated with each of the storage elements, with a first flag which is set if the associated storage element is in a process of being written to with data to be decoded or is full of data to be decoded which have not yet all been decoded, a second flag which is set if said associated storage element is full of data to be decoded which have not yet all been decoded, and a third flag which has a first value if said associated storage element contains data to be decoded from the first data stream and a second value if said associated storage element contains data to be decoded from the second data stream.

3. A block decoder according to claim 1 wherein the storage elements are single port RAM.

4. A block decoder according to claim 1 wherein the block decoding unit is configured to perform LDPC decoding.

5. A system, comprising:

a first demodulator to generate a first data stream to be decoded, and a second demodulator to generate a second data stream to be decoded; and

the block decoder according to claim 1 to decode the data from the first and second data streams.

6. The system according to claim 5 wherein the demodulators and block decoder comprise part of a satellite transmission receiver.

7. A process for block decoding, comprising:

receiving a first data stream to be decoded and at least a second data stream to be decoded distinct from said first data stream;

storing, in storage elements of an input memory of a block decoder, at least one block of data from the first data stream and at least one block of data from the second data stream;

block decoding, by the block decoder from the input memory, blocks of data from the first and second data streams; and

multiplexing blocks of data from the first data stream and blocks of data from the second data stream as input to the block decoding, by saving and reading said blocks in the storage elements of the input memory, wherein;

a sum of respective maximum bit rates of each of the first and second data streams is less than M, where M indicates a maximum input bit rate for the block decoding unit; and

the input memory includes at least four storage elements, each configured to store a block of data to be decoded, and used by order of priority or in a circular manner to store the data to be decoded from the first data stream and the data to be decoded from the second data stream.

8. A process for block decoding according to claim 7 wherein at least three flags are associated with each of the storage elements, with a first flag which is set if the associated storage element is in a process of being written to with data to be decoded or is full of data to be decoded which have not yet all been decoded, a second flag which is set if said associated storage element is full of data to be decoded which have not yet all been decoded, and a third flag which has a first value if said associated storage element contains data to be decoded from the first data stream and a second value if said associated storage element contains data to be decoded from the second data stream.

9. A process for block decoding according to claim 7 wherein the storage elements are single port RAM.

10. A process for block decoding according to claim 7 wherein the block decoding is LDPC decoding.

11. A system, comprising:

means for receiving a first data stream to be decoded and at least a second data stream to be decoded distinct from said first data stream;

means, including storage elements of an input memory of a block decoder, for storing at least one block of data from the first data stream and at least one block of data from the second data stream;

means, included in the block decoder from the input memory, for block decoding blocks of data from the first and second data streams; and

means for multiplexing blocks of data from the first data stream and blocks of data from the second data stream as input to the means for block decoding, by saving and reading said blocks in the storage elements of the input memory;

wherein;

a sum of respective maximum bit rates of each of the first and second data streams is less than M, where M indicates a maximum input bit rate for the means for block decoding; and

the input memory includes at least four storage elements, each configured to store a block of data to be decoded, and used by order of priority or in a circular manner to store the data to be decoded from the first data stream and the data to be decoded from the second data stream.

12. The system of claim 11, further comprising:

first demodulator means for generating the first data stream to be decoded; and

second demodulator means for generating the second data stream to be decoded.

13. The system of claim 11 wherein at least three flags are associated with each of the storage elements, with a first flag which is set if the associated storage element is in a process of being written to with data to be decoded or is full of data to be decoded which have not yet all been decoded, a second flag which is set if said associated storage element is full of data to be decoded which have not yet all been decoded, and a third flag which has a first value if said associated storage element contains data to be decoded from the first data stream and a second value if said associated storage element contains data to be decoded from the second data stream.

14. The system of claim 11 wherein at least some of said storage elements includes a single port RAM.

15. The system of claim 11 wherein the block decoder is configured to perform LDPC decoding.

16. An article of manufacture, comprising:

a machine-readable medium having instruction stored thereon that are executable by a processor to process a first data stream and to process a second data stream distinct from the first data stream, by;

storing, in storage elements of an input memory of a block decoder, at least one block of data from the first data stream and at least one block of data from the second data stream;

block decoding, by the block decoder from the input memory, blocks of data from the first and second data streams; and

multiplexing blocks of data from the first data stream and blocks of data from the second data stream as input to the block decoding, by saving and reading said blocks in the storage elements of the input memory, wherein;

a sum of respective maximum bit rates of each of the first and second data streams is less than M, where M indicates a maximum input bit rate for the block decoder; and

the input memory includes at least four storage elements, each configured to store a block of data to be decoded, and used by order of priority or in a circular manner to store the data to be decoded from the first data stream and the data to be decoded from the second data stream.

17. The article of manufacture of claim 16 wherein at least three flags are associated with each of the storage elements, with a first flag which is set if the associated storage element is in a process of being written to with data to be decoded or is full of data to be decoded which have not yet all been decoded, a second flag which is set if said associated storage element is full of data to be decoded which have not yet all been decoded, and a third flag which has a first value if said associated storage element contains data to be decoded from the first data stream and a second value if said associated storage element contains data to be decoded from the second data stream.

18. The article of manufacture of claim 16 wherein at least some of said storage elements includes a single port RAM.

19. The article of manufacture of claim 16 wherein the block decoder is configured to perform LDPC decoding.