Background thread processing in a multithread digital signal processor

• US 20070094660A1
• Filed: 10/20/2005
• Published: 04/26/2007
• Est. Priority Date: 10/20/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Codrescu, Lucian
• Granted Patent: US 7,913,255 B2
• Time in Patent Office: Days
• US Class Current: 718/100
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide background thread processing in a multithread digital signal processor for backgrounding and other background operations. The method and system form a background thread interrupt as one of a plurality of interrupt types, the background thread interrupt initiates a low-priority background process using one of a plurality of processing threads of a multithread digital signal processor. The process includes storing the background thread interrupt in an interrupt register and a background processing mask for associating with a processing thread of the multithread digital signal processor, which associates with at least a subset of said plurality of processing threads. Upon sensing a cache miss in one of the processing threads during multithread processing, the interrupt register issues the background thread interrupt and the digital signal processor initiates background processing using one of the processing threads having an associated background processing mask.

Claims

1. A method for performing background processing in a multithread digital signal processor comprising a plurality of processing threads, said method comprising the steps of:

forming a background thread interrupt as one of a plurality of interrupt types, said thread interrupt for initiating a background process using on of a plurality of processing threads of a multithread digital signal processor;

storing said background thread interrupt in a interrupt register;

forming a background processing mask for associating with a processing thread of said multithread digital signal processor;

associating said background processing mask with at least a subset of said plurality of processing threads;

sensing the presence of a predetermined event in one of said plurality of processing threads during multithread processing of said digital signal processor;

issuing said background thread interrupt from said interrupt register in response to said predetermined event; and

initiating background processing using a subset of said plurality of processing threads having an associated background process mask.

2. The method of claim 1, further comprising the step of steps of:

storing said background thread interrupt as a background prefetch interrupt;

forming said background processing mask as a background prefetch processing mask; and

initiating said background processing step as a background prefetch processing step.

3. The method of claim 1, further comprising the steps of:

forming said background thread interrupt as a low-priority thread interrupt for performing a low-priority background processing using said subset of said plurality of processing threads; and

issuing said low-priority thread interrupt upon the occurrence of said predetermined event.

4. The method of claim 1, further comprising the steps of:

sensing the presence of a cache miss as said predetermined event in one of said plurality of processing threads during multithread processing of said digital signal processor;

issuing said background thread interrupt from said interrupt register in response to said cache miss.

5. The method of claim 1, further comprising the step of forming said background thread interrupt as a data element of a translation lookaside buffer associated with digital signal processor.

7. The method of claim 1, further comprising the step of selecting said subset of said plurality of processing threads as idle ones of said plurality of processing threads.

8. The method of claim 1, further comprising the step of performing said background processing during interleaved multithreaded operation of said plurality of processing threads.

9. The method of claim 1, further comprising the step of terminating said background processing in said subset of said plurality of processing threads upon said interrupt register issuing an interrupt having a higher priority than said background processing interrupt.

6. The method of claim 6, further comprising the steps of changing said data element of said translation lookaside buffer according to varying operations on said digital signal processor.

10. A system for operation in association with a digital signal processor for processing interrupts arising in a multithreaded processor, comprising:

a background thread interrupt for operation as one of a plurality of interrupt types, said background thread interrupt for initiating a background process using one of a plurality of processing threads of a multithread digital signal processor;

an interrupt register for storing said background thread interrupt;

a background processing mask for associating with a processing thread of said multithread digital signal processor;

a mask register for associating said background processing mask with at least a subset of said plurality of processing threads;

event sensing instructions for sensing the presence of a predetermined event in one of said plurality of processing threads during multithread processing of said digital signal processor;

interrupt issuing instructions associated with said interrupt register for issuing said background thread interrupt from said interrupt register in response to said predetermined event; and

background processing circuitry for initiating background processing using one of said subset of said plurality of processing threads having an associated background process mask.

11. The system of claim 10, further comprising:

circuitry and instructions associated with said interrupt register for storing said background thread interrupt as a background prefetch interrupt;

circuitry and instructions associated with said mask register for forming said background processing mask as a background prefetch processing mask; and

background processing circuitry and instructions for initiating said background processing step as a background prefetch processing step.

12. The system of claim 10, further comprising:

processing instructions and circuitry for forming said background thread interrupt as a low-priority thread interrupt for performing a low-priority background processing using said subset of said plurality of processing threads; and

issuing instructions associated with said interrupt register for issuing said low-priority thread interrupt upon the occurrence of said predetermined event.

13. The system of claim 10, further comprising:

event sensing circuitry and instructions for sensing the presence of a cache miss as said predetermined event in one of said plurality of processing threads during multithread processing of said digital signal processor;

interrupt issuing circuitry and instructions for issuing said background thread interrupt from said interrupt register in response to said cache miss.

14. The system of claim 10, further comprising thread interrupt forming instructions for forming said background thread interrupt as a data element of a translation lookaside buffer associated with digital signal processor.

15. The system of claim 14, wherein said thread interrupt forming instructions further comprise instructions for changing said data element of said translation lookaside buffer according to varying operations on said digital signal processor.

16. The system of claim 15, further comprising thread selection circuitry and instructions for selecting said subset of said plurality of processing threads as idle ones of said plurality of processing threads.

17. The system of claim 10, wherein said processor further comprises processing instructions for performing said background processing during interleaved multithreaded operation of said plurality of processing threads.

18. The system of claim 10, wherein said processor further comprises processing circuitry and instructions for terminating said background processing in said subset of said plurality of processing threads upon said interrupt register issuing an interrupt having a higher priority than said background processing interrupt.

19. A digital signal processor for operation in support of a personal electronics device, said digital signal process comprising means for performing background processing, said background processing means comprising:

means for forming a background thread interrupt as one of a plurality of interrupt types, said background thread interrupt for initiating a background process using on of a plurality of processing threads of a multithread digital signal processor;

means for storing said background thread interrupt in a interrupt register;

means for forming a forming a background processing mask for associating with a processing thread of said multithread digital signal processor;

means for associating said background processing mask with at least a subset of said plurality of processing threads;

means for sensing the presence of a predetermined event in one of said plurality of processing threads during multithread processing of said digital signal processor;

means for issuing said background thread interrupt from said interrupt register in response to said predetermined event; and

means for initiating background processing using one of said subset of said plurality of processing threads having an associated background process mask.

20. The digital signal processor of system of claim 19, further comprising:

means for storing said background thread interrupt as a background prefetch interrupt;

means for forming said background processing mask as a background prefetch processing mask; and

means for initiating said background processing step as a background prefetch processing step.

21. The digital signal processor of system of claim 19, further comprising:

means for forming said background thread interrupt as a low-priority thread interrupt for performing a low-priority background processing using said subset of said plurality of processing threads; and

means for issuing said low-priority thread interrupt upon the occurrence of said predetermined event.

22. The digital signal processor of system of claim 19, further comprising means for forming said background thread interrupt as a data element of a translation lookaside buffer associated with digital signal processor.

23. The digital signal processor of system of claim 19, further comprising means for changing said data element of said translation lookaside buffer according to varying operations on said digital signal processor.

24. The digital signal processor of system of claim 19, further comprising means for selecting said subset of said plurality of processing threads as idle ones of said plurality of processing threads.

25. The digital signal processor of system of claim 19, further comprising means for performing said background processing during interleaved multithreaded operation of said plurality of processing threads.

26. The digital signal processor of system of claim 19, further comprising means for terminating said background processing in said subset of said plurality of processing threads upon said interrupt register issuing an interrupt having a higher priority than said background processing interrupt.

28. A computer usable medium having computer readable program code means embodied therein for performing background processing in a multithread digital signal processor comprising a plurality of processing threads, the computer usable medium comprising:

computer readable program code means for forming a background thread interrupt as one of a plurality of interrupt types, said background thread interrupt for initiating a background process using on of a plurality of processing threads of a multithread digital signal processor;

computer readable program code means for storing said background thread interrupt in a interrupt register;

computer readable program code means for forming a forming a background processing mask for associating with a processing thread of said multithread digital signal processor;

computer readable program code means for associating said background processing mask with at least a subset of said plurality of processing threads;

computer readable program code means for sensing the presence of a predetermined event in one of said plurality of processing threads during multithread processing of said digital signal processor;

computer readable program code means for issuing said background thread interrupt from said interrupt register in response to said predetermined event; and

computer readable program code means for initiating background processing using one of said subset of said plurality of processing threads having an associated background process mask.

29. The computer usable medium of claim 28, further comprising:

computer readable program code means for storing said background thread interrupt as a background prefetch interrupt;

computer readable program code means for forming said background processing mask as a background prefetch processing mask; and

computer readable program code means for initiating said background processing step as a background prefetch processing step.