Shared resource acquisition

• US 20070094669A1
• Filed: 10/25/2005
• Published: 04/26/2007
• Est. Priority Date: 10/25/2005
• Status: Abandoned Application

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Kishan, Arun, Marinescu, Adrian, Clift, Neill, Rector, John
• Application Number:
  US11/257,649
• Publication Number:
  US 20070094669A1
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A technology for exclusively acquiring a shared resource is disclosed. In one method approach, the method determines that a shared resource is available to be exclusively acquired by a first thread. The method also prevents partial execution of operations by a second thread, during operations to exclusively acquire the shared resource by the first thread, which may be accomplished by using an interrupt. The preventing of partial execution of operations by the second thread may be initiated by the first thread. The method embodiment then performs operations to exclusively acquire the shared resource by the first thread.

Claims

1. A computer-implemented method for exclusively acquiring a shared resource, said computer-implemented method comprising:

determining that said shared resource is available to be exclusively acquired by a first thread;

preventing partial execution of operations by a second thread to acquire said shared resource, during operations to exclusively acquire said shared resource by said first thread, wherein said preventing partial execution of operations by said second thread is initiated by said first thread; and

performing said operations to exclusively acquire said shared resource by said first thread.

2. The computer-implemented method as recited in claim 1 wherein said preventing partial execution of operations by a second thread comprises:

issuing an interrupt to a processor on which said second thread is running wherein said interrupt causes operations of said second thread to be either fully completed or prevented from being started prior to said performing said operations to exclusively acquire said shared resource by said first thread.

3. The computer-implemented method as recited in claim 2 wherein issuing an interrupt to a processor on which said second thread is running comprises:

issuing an Inter-processor Interrupt (IPI) to said processor on which said second thread is running.

4. The computer-implemented method as recited in claim 1 wherein said preventing partial execution of operations by a second thread comprises:

on a processor shared between said first thread and said second thread, causing operations on said second thread to be either fully completed or prevented from being started prior to removing said second thread from said processor and prior to performing said operations to exclusively acquire said shared resource by said first thread.

5. The computer-implemented method as recited in claim 1 wherein said computer-implemented method does not require the use of atomic instructions on corresponding shared acquisitions of any shared resources.

6. The computer-implemented method as recited in claim 1 wherein said computer-implemented method does not require altering of existing corresponding shared acquire methods.

7. A system for acquiring a shared resource, said system comprising:

a thread manager, said thread manager configured to determine when a shared resource is available to be exclusively acquired by a first thread;

an operation suspension module coupled to said thread manager, said operation suspension module preventing partial execution of operations by a second thread to acquire said shared resource, during operations to exclusively acquire said shared resource by said first thread; and

an exclusive acquisition module coupled to said operation suspension module, said exclusive acquisition module configured to perform said operations to exclusively acquire said shared resource by said first thread, said exclusive acquisition module further configured to initiate action by said operation suspension module.

8. The system of claim 7 wherein said operation suspension module comprises:

an interrupt issuing unit configured to issue an interrupt to a processor on which said second thread is running wherein said interrupt causes operations on said second thread to be either fully completed or prevented from being started prior to performing said operations to exclusively acquire said shared resource by said first thread.

9. The system of claim 8 wherein said interrupt issuing unit is configured to issue an Inter-processor Interrupt (IPI) to said processor on which said second thread is running.

10. The system of claim 7 wherein said operation suspension module is configured to cause operations on said second thread to be either fully completed or prevented from being started prior to removing said second thread from a processor shared with said first thread, and prior to performing said operations to exclusively acquire said shared resource by said first thread.

11. The system of claim 7 further comprising:

a shared acquisition module coupled with said exclusive acquisition module, said shared acquisition module configured to perform said operations to non-exclusively acquire said shared resource.

12. The system of claim 11 wherein said exclusive acquisition module is operable without the shared acquisition module using atomic instructions.

13. The system of claim 11 wherein said shared acquisition module is operable without requiring altering of existing shared acquire methods.

14. Instructions on a computer-usable medium wherein the instructions when executed cause a computer system to perform a shared resource acquisition method, said method comprising:

determining that said shared resource is available to be exclusively acquired by a first thread;

suspending actions by a second thread such that partial execution of operations by said second thread to acquire said shared resource are prevented during operations to exclusively acquire said shared resource by said first thread, wherein said suspending actions by said second thread is initiated by said first thread; and

performing said operations to exclusively acquire said shared resource by said first thread such that race conditions between said first thread and said second thread are avoided.

15. The instructions of claim 14 wherein said instructions which when executed cause said computer system to suspend actions by a second thread further comprise instructions which cause said computer system to:

issue an interrupt to a processor on which said second thread is running wherein said interrupt causes operations on said second thread to be either fully completed or prevented from being started prior to said performing said operations to exclusively acquire said shared resource by said first thread.

16. The instructions of claim 15 wherein said instructions which when executed cause said computer system to issue said interrupt to said processor in which said second thread is running further comprise instructions which cause said computer system to:

issue an Inter-processor Interrupt (IPI) to said processor on which said second thread is running.

17. The instructions of claim 14 wherein said instructions which when executed cause said computer system to suspend actions by a second thread further comprise instructions which cause said computer system to:

on a processor shared between said first thread and said second thread, cause operations on said second thread to be either fully completed or prevented from being started prior to removing said second thread from said processor and prior to performing said operations to exclusively acquire said shared resource by said first thread.

18. The instructions of claim 14 wherein said shared resource acquisition method performed by said computer system does not require imposing an additional burden on corresponding shared acquisitions of any shared resources.

19. The instructions of claim 14 wherein said shared resource acquisition method performed by said computer system does not require altering of existing corresponding shared acquire methods.

20. The instructions of claim 14 wherein said shared resource acquisition method performed by said computer system does not require utilizing atomic operations during corresponding shared acquisitions of any shared resources.