SILICON MEMS BASED TWO-PHASE HEAT TRANSFER DEVICE

• US 20070095507A1
• Filed: 09/08/2006
• Published: 05/03/2007
• Est. Priority Date: 09/16/2005
• Status: Active Grant

• Current Assignee: University of Cincinnati
• Original Assignee: University of Cincinnati
• Inventors: Shuja, Ahmed, Medis, Praveen, Parimi, Srinivas, Gerner, Frank, Henderson, H.
• Granted Patent: US 7,705,342 B2
• Time in Patent Office: Days
• US Class Current: 165/104.26
• CPC Class Codes: F28D 15/043 forming loops, e.g. capillary pumped loops
• CPC Class Codes: H01L 23/427 Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: Y10S 165/218 Condensor adapted to cover opening at top of vapor generator
• CPC Class Codes: Y10T 29/49396 Condenser, evaporator or vaporizer making

Abstract

The present invention is a MEMS-based two-phase LHP (loop heat pipe) and CPL (capillary pumped loop) using semiconductor grade silicon and microlithographic/anisotrophic etching techniques to achieve a planar configuration. The principal working material is silicon (and compatible borosilicate glass where necessary), particularly compatible with the cooling needs for electronic and computer chips and package cooling. The microloop heat pipes (μLHP™) utilize cutting edge microfabrication techniques. The device has no pump or moving parts, and is capable of moving heat at high power densities, using revolutionary coherent porous silicon (CPS) wicks. The CPS wicks minimize packaging thermal mismatch stress and improves strength-to-weight ratio. Also burst-through pressures can be controlled as the diameter of the coherent pores can be controlled on a sub-micron scale. The two phase planar operation provides extremely low specific thermal resistance (20-60W/cm²). The operation is dependent upon a unique micropatterened CPS wick which contains up to millions per square centimeter of stacked uniform micro-through-capillaries in semiconductor-grade silicon, which serve as the capillary “engine,” as opposed to the stochastic distribution of pores in the typical heat pipe wick. As with all heat pipes, cooling occurs by virtue of the extraction of heat by the latent heat of phase change of the operating fluid into vapor. In the cooling of a laptop computer processor the device could be attached to the processor during laptop assembly. Consistent with efforts to miniaturize electronics components, the current invention can be directly integrated with a unpackaged chip. For applications requiring larger cooling surface areas, the planar evaporators can be spread out in a matrix and integrally connected through properly sized manifold systems.

Claims

1. A device for cooling a heated surface, comprising:

an evaporator having a cap that is formed of a microprocessor grade silicon, the cap having a first surface that is adapted to be attached to a heated surface of an object;

the evaporator further including a wick structure having a porous surface;

the top cap further including one or more thermal conductors that extend away from a second surface of the cap and that have a distal portion in substantial proximity to the porous surface of the wick structure to define two or more evaporation chambers therebetween;

the evaporator further including a supply of cooling fluid contained within the wick structure, the cooling fluid being generally evenly distributed on the porous surface of the wick structure;

wherein the two or more evaporation chambers are connected to a condensation chamber defined within a condenser so that vaporized cooling fluid that is supplied to it from the evaporation chambers is converted to a liquid form, the liquid cooling fluid being supplied to the cooling fluid supply contained within the wick structure; and

wherein the two or more evaporation chambers are physically separate from the condensation chamber.

2. The cooling device of claim 1, wherein the two or more thermal conductors are in physical contact with the porous surface of the wick structure.

3. The cooling device of claim 1, wherein the wick structure comprises a mesh screen and a plurality of packed fibers.

4. The cooling device of claim 3, wherein the pack fibers comprise packed quartz fibers.

5. The cooling device of claim 1, wherein the wick structure includes a layer formed of coherent porous silicon, a first surface of the coherent porous silicon layer forming the porous surface of the wick structure, the pores being oriented in the coherent porous silicon plate so that cooling fluid from the cooling fluid supply in the wick structure is transported through the pores and to the first surface of the coherent porous silicon layer.

6. The cooling device of claim 5, further comprising a first interconnect that allows vapor to flow from the two or more evaporation chambers to the condensation chamber, and further comprising a second interconnect that allows cooling fluid to flow from the condensation chamber to the cooling fluid supply in the wick structure, at least one of the first and second interconnects being formed by an impact grinding process.

7. The cooling device of claim 5, wherein the wick structure further comprises a housing formed of a semiconductor grade silicon, and wherein the silicon housing, silicon top cap, and coherent porous silicon plate are bonded together by means of a metallurgical bonding technique.

8. The cooling device of claim 5, wherein the evaporator comprises a plurality of thermal conductors that extend into and beyond at least some of the pores defined in the coherent porous silicon plate.

9. The cooling device of claim 1, wherein the first surface of the top cap is curved.

10. The cooling device of claim 1, wherein the cooling device is integrally formed as a portion of an integrated circuit formed of silicon.