Forming a phase change memory with an ovonic threshold switch

• US 20070096090A1
• Filed: 10/28/2005
• Published: 05/03/2007
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Ovonyx Incorporated (Micron Technology, Inc.)
• Inventors: Dennison, Charles
• Granted Patent: US 8,188,454 B2
• Time in Patent Office: Days
• US Class Current: 257/42
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

Claims

1. A method comprising:

forming an ovonic threshold switch including a chalcogenide layer and a plug wherein the chalcogenide layer overlaps the plug on two opposed sides.

2. The method of claim 1 including forming an ovonic memory device underlying said ovonic threshold switch device.

3. The method of claim 2 including forming a common electrode between said ovonic memory device and ovonic threshold switch device.

4. The method of claim 3 including etching a stack of layers to form said ovonic threshold switch device.

5. The method of claim 4 including etching said common electrode during the same etch used to etch said stack.

6. The method of claim 5 including etching said common electrode using the same mask used to etch said stack.

7. The method of claim 6 including using a hard mask to etch said stack.

8. The method of claim 2 including forming said ovonic memory including a pore having a chalcogenide layer and an electrode in said pore.

9. The method of claim 2 including forming said ovonic memory with a pore filled with an electrode.

10. The method of claim 9 including forming said ovonic memory including a chalcogenide layer which is defined to have a dimension in common with said ovonic threshold switch device.

11. An apparatus comprising:

an ovonic threshold switch;

an ovonic memory under said ovonic threshold switch; and

said ovonic threshold switch including a lower electrode, a chalcogenide layer, an upper electrode, and an intervening dielectric, a conductor formed in said dielectric, said chalcogenide layer overhanging said conductor on two opposed sides.

12. The apparatus of claim 11 wherein said conductor is a plug.

13. The apparatus of claim 12 wherein said plug is formed in the dielectric including an insulator on either side of said plug, said insulator on either side of said plug underlying said overlying chalcogenide layer.

14. The apparatus of claim 13 wherein said ovonic threshold switch lower electrode, chalcogenide layer, and upper electrode are all formed with a common edge.

15. The apparatus of claim 14 including a common electrode between said switch and said memory.

16. The apparatus of claim 15 wherein said common electrode has a common edge with one or more layers of said ovonic threshold switch.

17. The apparatus of claim 16 wherein said memory includes a pore and a chalcogenide layer, said chalcogenide layer formed in said pore.

18. The apparatus of claim 16 wherein said memory includes an insulator with a pore formed in said insulator, said pore filled with a plug.

19. The apparatus of claim 18 including a common electrode over said pore and said insulator, said common electrode having dimensions corresponding to the dimensions of said ovonic threshold switch chalcogenide layer.

20. The apparatus of claim 11 wherein said ovonic threshold switch is formed as an etched stack having a common edge and said memory includes a lance, the overlap of said stack to said lance being greater than one-half the thickness of the chalcogenide layer of said ovonic threshold switch.

21. A system comprising:

a battery;

a processor; and

a memory coupled to said processor, said memory including a cell including an ovonic threshold switch and an ovonic memory under said ovonic threshold switch, said switch including a lower electrode, a chalcogenide layer, an upper electrode, and an intervening dielectric, a conductor formed in said dielectric, said chalcogenide layer overhanging said conductor on two opposed sides.

22. The system of claim 21 wherein said conductor is formed in the dielectric including an insulator on either side of said conductor, said insulator on either side of said conductor underlying said overlying chalcogenide layer.

23. The system of claim 22 wherein said switch lower electrode, chalcogenide layer, and upper electrode are all formed with a common edge.

24. The system of claim 23 including a common electrode between said switch and said ovonic memory.

25. The system of claim 25 wherein said common electrode has a common edge with one or more layers of said ovonic threshold switch.