Electronic device and semiconductor device and method for manufacturing the same

• US 20070096096A1
• Filed: 11/29/2004
• Published: 05/03/2007
• Est. Priority Date: 12/02/2003
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kuwabara, Hideaki, Maekawa, Shinji, Nakamura, Osamu, Yamazaki, Shunpei
• Granted Patent: US 7,575,965 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: Y02P 80/30 Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

It is conceivable that the problem that a signal is delayed by resistor of a wiring in producing a display which displays large area becomes remarkable. The present invention provides a manufacturing process using a droplet discharge method suitable for a large-sized substrate.

In the present invention, after forming a base layer 11 (or base pretreatment) which enhances adhesiveness over a substrate in advance and forming an insulating film, a mask having a desired pattern shape is formed, and a desired depression is formed by using the mask. A metal material is filled in the depression having a mask 13 and a sidewall made from an insulating film by a droplet discharge method to form an embedded wiring (a gate electrode, a capacitor wiring, lead wiring or the like. Afterwards, it is flattened by a planarization processing, for example, a press or a CMP processing.

Claims

1. A semiconductor device comprising:

a base layer formed over a substrate having an insulating surface;

an insulating layer and at least one of a gate wiring and a gate electrode formed over the base layer;

a gate insulating film formed over one of the gate wiring and the gate electrode; and

an active layer of a thin film transistor including at least a channel formation region over the gate insulating film;

a source wiring and an electrode formed over the active layer; and

a pixel electrode formed over the electrode,

wherein one of the gate wiring and the gate electrode contains a resin and has the same film thickness as that of the insulating layer.

2. A semiconductor device according to claim 1, wherein the base layer comprises a material selected from the group consisting of a transition metal, an oxide of said transition metal, a nitride of said transition metal, and an oxynitride of said transition metal.

3. A semiconductor device according to claim 2, wherein the transition metal comprises a material selected from the group consisting of Sc, Ti, Cr, Ni, V, Mn, Fe, Co, Cu, Zn.

4. A semiconductor device according to claim 1, wherein the active layer of the thin film transistor is a non-single crystalline semiconductor film or a polycrystalline semiconductor film added with hydrogen or halogen hydrogen.

5. A semiconductor device according to claim 1, the width of the gate electrode of the thin film transistor is from 5 μ

m to 100 μ

m.

6. A semiconductor device according to claim 1, wherein the length of the gate electrode width of the thin film transistor is shorter than that of the thickness of the gate electrode of the thin film transistor.

7. A semiconductor device according to claim 1, wherein a surface including an upper surface of the gate wiring or the gate electrode and a surface including an upper surface of the insulating layer are in the same plane.

8. A semiconductor device according to claim 1, wherein a P-V value of a projection and a depression on an upper surface of the insulating layer is less than 20 nm.

9. A semiconductor device according to claim 1, wherein P-V value of a projection and a depression on the upper surface of the gate wiring or gate electrode is lower than 20 nm.

10. A semiconductor device according to claim 1, further comprising:

a liquid crystal display device including a second substrate opposing to the substrate, and a liquid crystal interposed between a pair of substrates composed of the substrate and the second substrate.

11. A semiconductor device according to claim 1, further comprising a plurality of light emitting elements including a cathode, a layer containing an organic compound and a anode.

12. A semiconductor device according to claim 1, wherein the semiconductor device is an interactive video/audio communication device or a general-purpose remote control device.

13. A semiconductor device comprising:

an insulating layer and at least one of a gate wiring and a gate electrode formed over a substrate having an insulating surface;

a gate insulating film formed over one of the gate wiring and the gate electrode; and

an active layer of a thin film transistor including at least a channel formation region over the gate insulating film;

a source wiring and an electrode formed over the active layer; and

a pixel electrode formed over the electrode,

wherein one of the gate wiring and the gate electrode contains a resin and has the same film thickness as that of the insulating layer.

14. A semiconductor device according to claim 13, wherein the length of the gate electrode width of the thin film transistor is shorter than that of the thickness of the gate electrode of the thin film transistor.

15. A semiconductor device according to claim 13, wherein a surface including an upper surface of the gate wiring or the gate electrode and a surface including an upper surface of the insulating layer are in the same plane.

16. A semiconductor device according to claim 13, further comprising:

a liquid crystal display device including a second substrate opposing to the substrate, and a liquid crystal interposed between a pair of substrates composed of the substrate and the second substrate.

17. A semiconductor device according to claim 13, further comprising a plurality of light emitting elements including a cathode, a layer containing an organic compound and a anode.

18. A semiconductor device according to claim 13, wherein the semiconductor device is an interactive video/audio communication device or a general-purpose remote control device.

19. A method for manufacturing a semiconductor device comprising the steps of:

forming a base film or performing a base pretreatment over a substrate having an insulating surface;

forming an insulating film over the substrate;

forming a mask over the insulating film;

forming a depression by selectively etching the insulating film;

forming an embedded wiring in the depression by a droplet discharge method;

removing the mask;

performing a planarization processing to an upper surface of the embedded wiring;

forming a gate insulating film over the embedded wiring; and

forming a semiconductor film over the gate insulating film.

20. A method for manufacturing a semiconductor device according to claim 19, wherein the base layer is used as an etching stopper in the step of forming the depression by selectively etching the insulating film.

21. A method for manufacturing a semiconductor device according to claim 19, wherein the planarizing process is a press treatment, a heat press treatment or a CMP processing pressing the insulating film and the embedded wiring by a press unit.

22. A method for manufacturing a semiconductor device according to claim 19, wherein the planarization processing is a heat press treatment capable of heating and pressing at the same time to perform baking of the embedded wiring.

23. A method for manufacturing a semiconductor device according to claim 19, wherein the embedded wiring is at least one of a gate electrode and gate wiring of a thin film transistor.

24. A method for manufacturing a semiconductor device according to claim 19, wherein the step of forming a mask over the insulating film comprises a step of forming a first material layer and a second material layer surrounding the first material layer,

wherein the first material layer is soluble in a first solvent, and

wherein the second material layer is soluble in a second solvent, and

wherein the first material layer and the second material layer are formed with a device comprising a plurality of nozzles capable of discharging different materials:

and

a step of forming a mask comprising the first material film by removing the second material alone by the second solvent.

25. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating film over a substrate having an insulating surface;

forming a mask over the insulating film;

forming a depression by selectively etching the insulating film;

forming an embedded wiring in the depression by a droplet discharge method;

removing the mask;

performing a planarization processing to an upper surface of the embedded wiring;

forming a gate insulating film over the embedded wiring; and

forming a semiconductor film over the gate insulating film.

26. A method for manufacturing a semiconductor device according to claim 25, wherein the planarizing process is a press treatment, a heat press treatment or a CMP processing pressing the insulating film and the embedded wiring by a press unit.

27. A method for manufacturing a semiconductor device according to claim 25, wherein the planarization processing is a heat press treatment capable of heating and pressing at the same time to perform baking of the embedded wiring.

28. A method for manufacturing a semiconductor device according to claim 25, wherein the embedded wiring is at least one of a gate electrode and gate wiring of a thin film transistor.

29. A method for manufacturing a semiconductor device according to claim 25, wherein the step of forming a mask over the insulating film comprises a step of forming a first material layer and a second material layer surrounding the first material layer,

wherein the first material layer is soluble in a first solvent, and

wherein the second material layer is soluble in a second solvent, and

wherein the first material layer and the second material layer are formed with a device comprising a plurality of nozzles capable of discharging different materials:

and

a step of forming a mask comprising the first material film by removing the second material alone by the second solvent.