THIN-FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, LIQUID CRYSTAL DISPLAY PANEL HAVING THE SAME AND ELECTRO-LUMINESCENCE DISPLAY PANEL HAVING THE SAME

• US 20070096097A1
• Filed: 10/03/2006
• Published: 05/03/2007
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Oh, Min-Seok, Yang, Sung-Hoon, Kim, Byoung-June, Choi, Yong-Mo, Choi, Jae-HO
• Granted Patent: US 7,615,867 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate

Abstract

A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Claims

1. A thin-film transistor comprising:

a gate electrode formed on a base substrate;

an active layer formed on the gate electrode to cover the gate electrode;

a source electrode and a drain electrode formed on the active layer, the source electrode being spaced apart from the drain electrode by a predetermined distance; and

a buffer layer formed between the active layer and the source electrode, and between the active layer and the drain electrode, the buffer layer formed to suppress an oxidation of the active layer.

2. The thin-film transistor of claim 1, wherein the buffer layer comprises a plurality of layers, and wherein the buffer layer comprises a second material that is bonded with a first material in the active layer to form a compound.

3. The thin-film transistor of claim 2, wherein the second material has a substantially continuously varying layer content ratio corresponding to a thickness of the buffer layer.

4. The thin-film transistor of claim 3, wherein the buffer layer comprises a first connection layer, a second connection layer, and a third connection layer.

5. The thin-film transistor of claim 4, wherein the first connection layer comprises a compound of the first material and the second material, wherein the second connection layer comprises the second material, and wherein the third connection layer comprises a compound of the second material and a third material.

6. The thin-film transistor of claim 5, wherein a content of the first material is substantially continuously decreased and a content of the second material is substantially continuously increased as a thickness of the first connection layer is increased, and wherein the content of the second material is substantially continuously decreased and a content of the third material is substantially continuously increased as a thickness of the third connection layer is increased.

7. The thin-film transistor of claim 6, wherein the first material comprises silicon.

8. The thin-film transistor of claim 6, wherein the second material comprises one of titanium, molybdenum, or nickel.

9. The thin-film transistor of claim 6, wherein the third material comprises nitrogen.

10. The thin-film transistor of claim 6, wherein the active layer comprises a semiconductor layer and an impurity layer.

11. The thin-film transistor of claim 10, wherein the semiconductor layer comprises amorphous silicon, and wherein the impurity layer comprises amorphous silicon heavily doped with ions.

12. The thin-film transistor of claim 4, wherein a thickness of the first connection layer is in a range of between about 50 Å

to about 150 Å

, wherein a thickness of the second connection layer is in a range of between about 100 Å

to about 500 Å

, and wherein a thickness of the third connection layer is in a range of between about 100 Å

to about 500 Å

.

13. A method of manufacturing a thin-film transistor comprising:

forming a gate electrode on a base substrate;

forming a gate insulation layer on the substrate to cover the gate electrode;

forming an active layer on the gate insulation layer to cover the gate electrode;

forming a buffer layer on the active layer to suppress an oxidation of the active layer;

primarily etching first predefined portions of the buffer layer and the active layer;

forming a source electrode and a drain electrode on the primarily etched active layer, wherein the source electrode and the drain electrode are separated from each other by a predetermined distance; and

secondarily etching second predefined portions of the buffer layer and the active layer, using as an etching mask at least one of the source electrode and the drain electrode.

14. The method of claim 13, wherein the buffer layer comprises a plurality of films formed by an in-situ process on the active layer.

15. The method of claim 14, wherein the buffer layer comprises a first connection layer, a second connection layer, and a third connection layer.

16. The method of claim 15, wherein the active layer comprises silicon.

17. The method of claim 16, wherein the first connection layer comprises titanium silicide, wherein the second connection layer comprises titanium, and wherein the third connection layer comprises titanium nitride.

18. The method of claim 17, wherein the first connection layer is formed by introducing hydrogen gas, silane gas, and titanium chloride gas into a chamber, wherein the second connection layer is formed by introducing hydrogen gas and titanium chloride gas into the chamber, and wherein the third connection layer is formed by introducing hydrogen gas, titanium chloride gas, and ammonia gas into the chamber.

19. The method of claim 18, wherein a flow rate of the silane gas is gradually decreased and a flow rate of the titanium chloride gas is gradually increased when forming the first connection layer, and wherein a flow rate of the titanium chloride gas is gradually decreased and a flow rate of the ammonia gas is gradually increased when forming the third connection layer.

20. The method of claim 16, wherein the first connection layer comprises molybdenum silicide, wherein the second connection layer comprises molybdenum, and wherein the third connection layer comprises molybdenum nitride.

21. The method of claim 20, wherein the first connection layer is formed by introducing hydrogen gas, silane gas, and molybdenum chloride gas into a chamber, wherein the second connection layer is formed by introducing hydrogen gas and molybdenum chloride gas into the chamber, and wherein the third connection layer is formed by introducing hydrogen gas, molybdenum chloride gas, and ammonia gas into the chamber.

22. The method of claim 21, wherein a flow rate of the silane gas is gradually decreased and a flow rate of the molybdenum chloride gas is gradually increased when forming the first connection layer, and wherein a flow rate of the molybdenum chloride gas is gradually decreased and a flow rate of the ammonia gas is gradually increased when forming the third connection layer.

23. The method of claim 13, further comprising:

primarily etching the first predefined portions of the buffer layer; and

using the primarily etched buffer layer as an etching mask, primarily etching the first predefined portions of the active layer.

24. The method of claim 13, wherein etching the first predefined portions of the buffer layer is performed using a chlorine-containing gas.

25. The method of claim 13, wherein etching the first predefined portions of the active layer is performed using a fluorine-containing gas.

26. The method of claim 25, wherein the active layer comprises a semiconductor layer and an impurity layer, and wherein secondarily etching the second predefined portions of the active layer is performed on predefined portions of the impurity layer.

27. A liquid crystal display panel comprising:

a first substrate having a thin-film transistor;

a second substrate disposed to face the first substrate; and

a liquid crystal layer interposed between the first substrate and the second substrate,

wherein the thin-film transistor comprises;

a gate electrode formed on the first substrate;

an active layer formed on the gate electrode to cover the gate electrode;

a source electrode and a drain electrode formed on the active layer, the source electrode being separated from the drain electrode by a predetermined distance; and

a buffer layer formed between the active layer and the source electrode, and between the active layer and the drain electrode, the buffer layer formed to suppress an oxidation of the active layer.

28. The liquid crystal display panel of claim 27, wherein the buffer layer comprises a plurality of layers, wherein the buffer layer comprises a second material that is bonded with a first material in the active layer to form a compound and wherein the second material has a substantially continuously varying layer content ratio corresponding to a thickness of the buffer layer.

29. An electro-luminescence display panel comprising:

a base substrate;

a switching thin-film transistor formed on the base substrate;

a driving thin-film transistor formed on the base substrate, the driving thin film transistor electrically connected to the switching thin-film transistor; and

an electro-luminescence device connected to the driving thin-film transistor, and configured to generate a light,

wherein the driving thin-film transistor comprises;

a driving gate electrode formed on the base substrate;

a driving active layer formed on the driving gate electrode to cover the driving gate electrode;

a driving source electrode and a driving drain electrode formed on the driving active layer and separated by a predetermined distance; and

a driving buffer layer formed between the driving active layer and the driving source electrode, and between the driving active layer and the driving drain electrode, the driving buffer layer formed to suppress an oxidation of the driving active layer.

30. The electro-luminescence display panel of claim 29, wherein the switching thin-film transistor comprises:

a switching gate electrode formed on the base substrate;

a switching active layer formed on the switching gate electrode to cover the switching gate electrode; and

a switching source electrode and a switching drain electrode formed on the switching active layer, wherein the switching source electrode and the switching drain electrode are separated by a predetermined distance.

31. The electro-luminescence display panel of claim 30, wherein the switching drain electrode is electrically connected to the driving gate electrode.

32. The electro-luminescence display panel of claim 30, wherein the driving buffer layer and the switching buffer layer comprise a plurality of layers, wherein the driving buffer layer and the switching buffer layer comprise a second material that is bonded with a first material in the driving active layer and the switching active layer to form a compound, and wherein the second material in the driving buffer layer and the switching buffer layer has a substantially continuously varying layer content ratio corresponding to a respective thickness of the driving buffer layer and the switching buffer layer.