Semiconductor devices with dielectric layers and methods of fabricating same

• US 20070096107A1
• Filed: 11/03/2005
• Published: 05/03/2007
• Est. Priority Date: 11/03/2005
• Status: Abandoned Application

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Brown, Dale
• Application Number:
  US11/265,919
• Publication Number:
  US 20070096107A1
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Abstract

A SiC semiconductor device with a SiC layer and an insulating layer is provided. The insulating layer may include glass or ceramic. The thermal expansion coefficient of the insulating layer may be matched to that of SiC to reduce stress at the interface. A method of processing the SiC semiconductor device is also provided.

Claims

1. A semiconductor device comprising:

at least one silicon carbide layer; and

an insulating layer disposed over the silicon carbide layer, wherein the insulating layer comprises glass or ceramic material.

2. The semiconductor device of claim 1, wherein the glass material comprises borosilicate glass or phosphosilicate glass.

3. The semiconductor device of claim 1, wherein the ceramic material comprises an oxide of aluminum, an oxide of arsenic, an oxide of antimony or an oxide of germanium in combination with SiO₂ and any combinations thereof.

4. The semiconductor device of claim 1, the device comprising a MOSFET or an integrated circuit or an electrooptical device or an insulated gate bipolar transistor or any combinations thereof.

5. The semiconductor device of claim 1, the device comprising a MOSFET device, wherein the insulating layer comprises a gate dielectric layer.

6. The semiconductor device of claim 1, the device comprising a MOSFET device, wherein the silicon carbide layer comprises a channel layer.

7. A semiconductor device comprising:

a silicon carbide layer; and

an insulating material layer disposed over the silicon carbide layer, wherein a thermal expansion coefficient of the insulating material is matched to a thermal expansion coefficient of the silicon carbide to reduce stress at a silicon carbide layer-insulating material layer interface.

8. The semiconductor device of claim 7, wherein the silicon carbide layer comprises a plurality of silicon carbide layers.

9. The semiconductor device of claim 7, wherein the insulating material layer comprises a graded or a layered structure.

10. The semiconductor device of claim 7, wherein the insulating material comprises a glass material or a ceramic material.

11. The semiconductor device of claim 7, wherein the insulating material comprises a borosilicate glass, or a phosphosilicate glass or an oxide of arsenic, antimony or germanium in combination with SiO₂ or any combinations thereof.

12. The semiconductor device of claim 7, wherein the thermal expansion coefficient of the insulating material is in a range of about 2×

10<sup>−

6</sup>/K to about 9×

10<sup>−

6</sup>/K.

13. The semiconductor device of claim 7, wherein the thermal expansion coefficient of the insulating material is in a range of about 3×

10<sup>−

6</sup>/K to about 7×

10<sup>−

6</sup>/K.

14. The semiconductor device of claim 7, wherein the thermal expansion coefficient of the insulating material is in a range of about 4×

10<sup>−

6</sup>/K to about 6×

10<sup>−

6</sup>/K.

15. The semiconductor device of claim 7, the device comprising a MOSFET or an integrated circuit or an electrooptical device or an insulated gate bipolar transistor or any combinations thereof.

16. The semiconductor device of claim 7, the device comprising a MOSFET device, wherein the silicon carbide layer comprises a channel layer.

17. The semiconductor device of claim 7, the device comprising a MOSFET device, wherein the insulating material layer comprises a gate dielectric layer.

18. A method of fabricating a silicon carbide device comprising:

providing a silicon carbide layer; and

providing an insulating layer over the silicon carbide layer;

wherein the insulating layer comprises a glass material or a ceramic material.

19. The method of claim 18, wherein providing the insulating layer comprises:

thermally oxidizing the silicon carbide layer; and

annealing the silicon carbide layer in an inert or oxidizing ambient.

20. The method of claim 19, wherein thermally oxidizing the silicon carbide layer comprises thermally oxidizing the silicon carbide layer in presence of glass forming agents or ceramic forming agents.

21. The method of claim 20, wherein the glass forming agents and ceramic forming agents comprise materials comprising phosphine, borane, diborane, trimethyl borate, trimethyl phosphate, phosphorus oxychloride, gaseous compounds of arsenic, aluminum, antimony, germanium and any combinations thereof.

22. The method of claim 18, wherein providing the insulating layer comprises depositing a thin film insulating layer.

23. The method of claim 22, wherein depositing the thin film comprises chemical vapor deposition, or laser assisted molecular beam deposition, or plasma enhanced chemical vapor deposition or sputtering or any combinations thereof.

24. The method of claim 22, wherein depositing the thin film further comprises using glass forming agents or ceramic forming agents comprising borane, diborane, phosphine, trimethyl borate, trimethyl phosphate, phosphorus oxychloride, oxides of arsenic, aluminum, antimony, germanium and any combinations thereof.

25. The method of claim 18, further comprising modifying a thermal expansion coefficient of the insulating layer to match a thermal expansion coefficient of the silicon carbide layer.

26. The method of claim 18, wherein the insulating layer comprises a graded structure or a layered structure.

27. The method of claim 18, further comprising:

providing a plurality of layers of silicon carbide;

patterning the silicon carbide to form a plurality of gate region grooves;

filling the plurality of gate region grooves with the insulating material;

patterning to form the source and drain regions; and

providing a plurality of metal contact layers.