Semiconductor device and method for fabricating the same

• US 20070096184A1
• Filed: 10/11/2006
• Published: 05/03/2007
• Est. Priority Date: 10/27/2005
• Status: Active Grant

• Current Assignee: Advanced Integrated Circuit Process LLC (AMTL LLC)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Akamatsu, Susumu
• Granted Patent: US 7,737,510 B2
• Time in Patent Office: Days
• US Class Current: 257/300
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A gate insulating film and a gate electrode are formed on an active region of a semiconductor substrate. A sidewall forming an L shape in cross section is formed on the sides of the gate electrode. Source/drain regions are formed in regions of the semiconductor substrate located outside an area covering the gate electrode and the sidewall. A stress-applying stress liner film is formed to cover the gate electrode and the sidewall.

Claims

1. A semiconductor device having a MIS transistor, said MIS transistor comprising:

a first gate insulating film formed on a semiconductor substrate;

a first gate electrode formed on the first gate insulating film;

a first sidewall covering the sides of the first gate electrode and the top surface of part of the semiconductor substrate and made of an insulating film forming an L shape in cross section;

first source/drain regions formed in regions of the semiconductor substrate located outside an area covering the first gate electrode and the first sidewall; and

a stress-applying insulating film covering the first gate electrode and the first sidewalls.

2. The semiconductor device of claim 1, wherein

the semiconductor substrate is made of silicon, and

a gate length direction of the first gate electrode is along a <

100>

orientation of the silicon.

3. The semiconductor device of claim 1, wherein

silicide layers are formed in an upper portion of the first gate electrode and respective upper portions of the first source/drain regions.

4. The semiconductor device of claim 1, wherein

a second sidewall forming a plate-like shape in cross section are formed between the first gate electrode and the first sidewall.

5. The semiconductor device of claim 1, wherein

SD extension diffusion regions are formed in regions of the semiconductor substrate located under the first sidewall.

6. The semiconductor device of claim 1, wherein

the MIS transistor is an N-type MIS transistor, and

the stress-applying insulating film has a tensile stress.

7. The semiconductor device of claim 6 further comprising

a P-type MIS transistor,

wherein the P-type MIS transistor comprises:

a second gate insulating film formed on the semiconductor substrate;

a second gate electrode formed on the second gate insulating film;

a third sidewall formed on the sides of the second gate electrode and forming an L shape in cross section;

a four sidewall formed on the third sidewall; and

second source/drain regions formed in regions of the semiconductor substrate located outside an area covering the second gate electrode and the third sidewall.

8. The semiconductor device of claim 7 further comprising:

an interlayer dielectric covering the N-type MIS transistor and the P-type MIS transistor; and

a contact passing through the interlayer dielectric and reaching the second source/drain regions of the P-type MIS transistor,

wherein the contact comes into contact with the fourth sidewall.

9. The semiconductor device of claim 6, wherein

the N-type MIS transistor and the P-type MIS transistor form an SRAM.

10. The semiconductor device of claim 1, wherein

the MIS transistor is a P-type MIS transistor, and

the stress-applying insulating film has a compressive stress.

11. A method for fabricating a semiconductor device including a MIS transistor having a first gate insulating film and a first gate electrode, said method comprising the steps of:

(a) forming a first insulating film covering the top surface of the first gate electrode and the top surface of a semiconductor substrate and a second insulating film covering the first insulating film;

(b) subjecting the first and second insulating films to anisotropic etching, thereby forming, on the sides of the first gate electrode, a first sidewall formed of part of the first insulating film and a second sidewall formed of part of the second insulating film;

(c) implanting ions into the semiconductor substrate using the first gate electrode, the first sidewalls and the second sidewalls as masks, thereby forming first source/drain regions in the semiconductor substrate;

(d) after the step (c), selectively removing the second sidewall; and

(e) after the step (d), forming a stress-applying insulating film to cover the first sidewall.

12. The method of claim 11, wherein

the semiconductor substrate is made of silicon, and

a gate length direction of the first gate electrode is along a <

100>

orientation of the silicon.

13. The method of claim 11, wherein

in the step (d), the second sidewall is removed by being etched on conditions that the second sidewall is given a higher etching selectivity than the first sidewall.

14. The method of claim 11, wherein

in the step (b), the first sidewall forms an L shape in cross section.

15. The method of claim 11 further comprising the step of

after the step (c), forming silicide layers in an upper portion of the first gate electrode and respective upper portions of the first source/drain regions.

16. The method of claim 11 further comprising the step of

before the step (a), forming a third sidewall forming a plate-like shape in cross section on the sides of the first gate electrode,

wherein in the step (a), the first insulating film is formed to cover the first gate electrode and the third sidewall.

17. The method of claim 11 further comprising the step of

implanting ions into the semiconductor substrate using the first gate electrode as a mask, thereby forming SD extension diffusion regions in the semiconductor substrate.

18. The method of claim 11, wherein

the MIS transistor is an N-type MIS transistor, and

a film having a tensile stress is formed as the stress-applying insulating film.

19. The method of claim 18, wherein

the semiconductor device further includes a P-type MIS transistor having a second gate insulating film and a second gate insulating film,

in the step (a), the first insulating film and the second insulating film are formed to cover also the second gate electrode,

in the step (b), the first and second insulating films are subjected to anisotropic etching, thereby further forming, on the sides of the second gate electrode, a fourth sidewall formed of part of the first insulating film and a fifth sidewall formed of part of the second insulating film,

the method further comprises the step of implanting ions into the semiconductor substrate using the second gate electrode and the fourth and fifth sidewalls as masks, thereby forming second source/drain regions in the semiconductor substrate,

in the step (d), the fifth sidewall is left without being removed, and

in the step (e), the stress-applying insulating film is formed to cover the fifth sidewall.

20. The method of claim 19 further comprising the steps of:

(f) after the step (e), forming an interlayer dielectric to cover the stress-applying insulating film;

(g) forming contact holes to pass through the interlayer dielectric and reach the second source/drain regions; and

(h) filling the contact holes with a conductor,

wherein in the step (g), part of the stress-applying insulating film covering the fifth sidewall are removed, thereby forming the contact holes.

21. The method of claim 19, wherein

the N-type MIS transistor and the P-type MIS transistor form an SRAM.

22. The method of claim 11, wherein

the MIS transistor is an N-type MIS transistor, and

a film having a compressive stress is formed as the stress-applying insulating film.