Method of manufacturing symmetric arrays

• US 20070096199A1
• Filed: 09/07/2006
• Published: 05/03/2007
• Est. Priority Date: 09/08/2005
• Status: Abandoned Application

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Lusky, Eli
• Application Number:
  US11/516,617
• Publication Number:
  US 20070096199A1
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements, generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas. A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area and bit line oxides whose height is at least a quarter of the distance between neighboring bit line oxides.

Claims

1. A non-volatile memory device comprising:

a plurality of word line areas each separated from its neighbor by a contact area;

an oxide-nitride-oxide (ONO) layer within said word line areas and at least partially within said contact areas; and

protective elements, generated when spacers are formed in the periphery area, to protect silicon under said ONO layer in said contact areas.

2. The device according to claim 1 and wherein said protective elements are formed of one of the following:

oxide, nitride and oxide-nitride-oxide.

3. The device according to claim 1 and wherein said spacers are formed of liners of 50-150 nm thick.

4. The device according to claim 1 and wherein said word line areas comprise Salicided word lines.

5. The device according to claim 1 and wherein said word line areas comprise silicided word lines.

6. The device according to claim 4 and wherein said word lines are Salicided with Copper silicide.

7. The device according to claim 4 and wherein said word lines are Salicided with Nickel silicide.

8. The device according to claim 5 and wherein said word lines are silicided with Tungsten silicide.

9. A non-volatile memory device comprising:

a plurality of word line areas each separated from its neighbor by a contact area; and

bit line oxides whose height is at least a quarter of the distance between neighboring bit line oxides.

10. The device according to claim 9 and also comprising protective elements at least between said bit line oxides in said contact area.

11. The device according to claim 10 and wherein said protective elements are formed of one of the following:

oxide, nitride and oxide-nitride-oxide.

12. The device according to claim 11 and wherein said word line areas comprise Salicided word lines.

13. The device according to claim 11 and wherein said word line areas comprise silicided word lines.

14. The device according to claim 12 and wherein said word lines are Salicided with Copper silicide.

15. The device according to claim 12 and wherein said word lines are Salicided with Nickel silicide.

16. The device according to claim 11 and wherein said word lines are silicided with Tungsten silicide.