Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon

• US 20070096201A1
• Filed: 06/19/2006
• Published: 05/03/2007
• Est. Priority Date: 10/31/2005
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Ning, Xian
• Granted Patent: US 7,820,500 B2
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method for forming a CMOS integrated circuit using strained silicon technology. The method forms a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region. In a preferred embodiment, the method patterns A spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges and to form the second sidewall spacer structures on the second gate structure, including the second edges, while using a portion of the liner layer as a stop layer. The method maintains the liner layer overlying the first source/drain regions and second source/drain regions during at least the patterning of the spacer dielectric layer according to a preferred embodiment. The method also etches a first source region and a first drain region adjacent to the first gate structure using the hard mask layer and the first sidewall spacers as a protective layer. The method deposits a silicon germanium fill material into the first source region and the first drain region to fill the etched first source region and the etched first drain region while causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region.

Claims

1. A method for forming a semiconductor integrated circuit device comprising:

providing a semiconductor substrate including a first well region and a second well region;

forming a dielectric layer overlying the semiconductor substrate including the first well region and the second well region;

forming a polysilicon gate layer overlying the dielectric layer, the polysilcon gate layer being overlying a first channel region in the first well region and a second channel region in the second well region in the semiconductor substrate;

forming a hard mask overlying the polysilicon gate layer;

patterning the polysilicon gate layer, including the hard mask layer, to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region;

forming a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region;

forming a spacer dielectric layer overlying the liner layer;

patterning the spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges and to form the second sidewall spacer structures on the second gate structure, including the second edges, while using a portion of the liner layer as a stop layer;

maintaining the liner layer overlying the first source/drain regions and second source/drain regions during at least the patterning of the spacer dielectric layer;

protecting the second well region including the second gate structure using a masking layer;

etching a first source region and a first drain region adjacent to the first gate structure using the hard mask layer and the first sidewall spacers as a protective layer;

depositing a silicon germanium fill material into the first source region and the first drain region to fill the etched first source region and the etched first drain region while causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region.

2. The method of claim 1 wherein the dielectric layer is less than 300 Angstroms.

3. The method of claim 1 wherein a portion of the liner layer masks a portion of the second well region during deposition of the silicon germanium material.

4. The method of claim 1 wherein the semiconductor substrate is essential silicon material.

5. The method of claim 1 wherein the silicon germanium material is single crystalline.

6. The method of claim 1 wherein the silicon germanium has a ratio of silicon/germanium of 10% to 20%.

7. The method of claim 1 further comprising removing the hard mask and any remaining portion of the liner layer and selectively forming silicide regions overlying the first gate structure, second gate structure, first source/drain regions, and second source/drain regions.

8. The method of claim 1 wherein the hard mask is a thickness of about 200 to about 400 Angstroms.

9. The method of claim 1 wherein the depositing is provided using an epitaxial reactor.

10. The method of claim 1 wherein the compressive mode increases a mobility of holes in the first channel region.

11. The method of claim 1 wherein the liner layer comprises a TEOS material.

12. The method of claim 1 wherein the spacer dielectric layer comprises an oxide bearing material.

13. The method of claim 1 wherein the spacer dielectric layer comprises an oxide on nitride on oxide material.

14. The method of claim 1 wherein the spacer dielectric layer comprises an oxide on nitride material.

15. The method of claim 1 wherein the liner layer has a thickness of about 100 Angstroms to greater than about 150 Angstroms.

16. A method for forming a semiconductor integrated circuit device comprising:

providing a semiconductor substrate including a first well region and a second well region;

forming a dielectric layer overlying the semiconductor substrate including the first well region and the second well region;

forming a polysilicon gate layer overlying the dielectric layer, the polysilcon gate layer being overlying a first channel region in the first well region and a second channel region in the second well region in the semiconductor substrate;

forming a hard mask overlying the polysilicon gate layer;

patterning the polysilicon gate layer, including the hard mask layer, to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region;

forming a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region;

forming a spacer dielectric layer overlying the liner layer;

patterning the spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges and to form the second sidewall spacer structures on the second gate structure, including the second edges, while using a portion of the liner layer as a stop layer;

maintaining the liner layer overlying the first source/drain regions and second source/drain regions during at least the patterning of the spacer dielectric layer;

protecting the second well region including the second gate structure using a masking layer overlying the second well region;

etching a first source region and a first drain region adjacent to the first gate structure using the hard mask layer and the first sidewall spacers as a protective layer;

stripping the masking layer overlying the second well region while exposing a portion of the liner layer overlying the second well region;

selectively depositing a silicon germanium fill material into the first source region and the first drain region to fill the etched first source region and the etched first drain region while using the portion of the liner layer overlying the second well region as a masking material; and

causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region.

17. The method of claim 16 wherein the liner layer comprises a TEOS material.

18. The method of claim 16 wherein the liner layer comprises a thickness ranging from about 100 Angstroms to greater than about 150 Angstroms.

19. The method of claim 16 wherein the first channel region has a length of about 65 nanometers and less.

20. The method of claim 16 wherein the masking layer comprises a photo masking material.