Semiconductor device and a method for manufacturing the same

• US 20070096224A1
• Filed: 12/07/2006
• Published: 05/03/2007
• Est. Priority Date: 10/01/1993
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Teramoto, Satoshi, Takemura, Yasuhiko
• Granted Patent: US 7,301,209 B2
• Time in Patent Office: Days
• US Class Current: 257/408
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges therein is provided on at least the high resistivity region so that N-type conductivity is induced in the high resistivity region. Accordingly, the reliability of N-channel type TFT against hot electrons can be improved.

Claims

1. A semiconductor device comprising:

a pixel portion comprising a first thin film transistor; and

a driver circuit comprising a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor comprising;

a silicon island over a substrate having an insulating surface, said silicon island comprising a source, a drain, and a channel located between said source and said drain;

a gate electrode provided adjacent to the channel with a gate insulating layer interposed therebetween;

an impurity region having a lower concentration of the impurity than concentrations of the source and the drain provided between the channel and at least one of the source and the drain;

a layer comprising silicon nitride over the gate electrode and the silicon island, said layer having a portion in contact with the gate insulating layer;

wherein the gate insulating layer has a first portion over the channel and a second portion over the impurity region and a thickness of the second portion is thinner than a thickness of the first portion, and

wherein the first thin film transistor has a pixel electrode electrically connected to one of the source and the drain.

9. A semiconductor device according to claim 1, wherein the gate insulating film comprises silicon oxide.

17. A semiconductor device according to claim 1, wherein a thickness of the gate insulating film is 500 Å

or less.

25. A semiconductor device according to claim 1, wherein the pixel electrode comprises ITO.

33. A semiconductor device according to claim 1, wherein the gate electrode and the impurity region of the second thin film transistor slightly overlap each other.

39. A semiconductor device according to claim 1, wherein a width of the high impurity of the first thin film transistor is wider than a width of the impurity region of the second thin film transistor.

45. A semiconductor device according to claim 1, wherein the first thin film transistor is an N-channel type thin film transistor.

53. A semiconductor device according to claim 1, wherein the first thin film transistor is a P-channel type thin film transistor.

2. A semiconductor device comprising:

a pixel portion comprising a first thin film transistor; and

a driver circuit comprising a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor comprising;

a silicon island over a substrate having an insulating surface, said silicon island comprising a source, a drain, and a channel located between said source and said drain;

a gate electrode provided adjacent to the channel with a gate insulating layer interposed therebetween;

an impurity region having a lower concentration of the impurity than concentrations of the source and the drain provided between the channel and at least one of the source and the drain; and

a layer comprising silicon nitride over the gate electrode and the silicon island, said layer having portions in contact with the gate insulating layer, the source, and drain respectively,

wherein the gate insulating layer has a first portion over the channel and a second portion over the impurity region and a thickness of the second portion is thinner than a thickness of the first portion,

wherein the first thin film transistor has a pixel electrode electrically connected to one of the source and the drain.

10. A semiconductor device according to claim 2, wherein the gate insulating film comprises silicon oxide.

18. A semiconductor device according to claim 2, wherein a thickness of the gate insulating film is 500 Å

or less.

26. A semiconductor device according to claim 2, wherein the pixel electrode comprises ITO.

34. A semiconductor device according to claim 2, wherein the gate electrode and the impurity region of the second thin film transistor slightly overlap each other.

40. A semiconductor device according to claim 2, wherein a width of the impurity region of the first thin film transistor is wider than a width of the impurity region of the second thin film transistor.

46. A semiconductor device according to claim 2, wherein the first thin film transistor is an N-channel type thin film transistor.

54. A semiconductor device according to claim 2, wherein the first thin film transistor is a P-channel type thin film transistor.

3. A semiconductor device comprising:

a pixel portion comprising a first thin film transistor; and

a driver circuit comprising a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor comprising;

a silicon island over a substrate having an insulating surface, said silicon island comprising a source, a drain, and a channel located between said source and said drain;

a gate electrode provided adjacent to the channel with a gate insulating layer interposed therebetween;

an impurity region having a lower concentration of the impurity than concentrations of the source and the drain provided between the channel and at least one of the source and the drain; and

a layer comprising silicon nitride over the gate electrode and the silicon island, said layer having a portion in contact with the gate insulating layer,

wherein the gate insulating layer covers the channel, source, and the drain, and

wherein the gate insulating layer has a first portion over the channel and a second portion over at least one of the source and the drain and a thickness of the second portion is thinner than a thickness of the first portion, and

wherein the first thin film transistor has a pixel electrode electrically connected to one of the source and the drain.

11. A semiconductor device according to claim 3, wherein the gate insulating film comprises silicon oxide.

19. A semiconductor device according to claim 3, wherein a thickness of the gate insulating film is 500 Å

or less.

27. A semiconductor device according to claim 3, wherein the pixel electrode comprises ITO.

35. A semiconductor device according to claim 3, wherein the gate electrode and the impurity region of the second thin film transistor slightly overlap each other.

41. A semiconductor device according to claim 3, wherein a width of the impurity region of the first thin film transistor is wider than a width of the impurity region of the second thin film transistor.

47. A semiconductor device according to claim 3, wherein the first thin film transistor is an N-channel type thin film transistor.

55. A semiconductor device according to claim 3, wherein the first thin film transistor is a P-channel type thin film transistor.

4. A semiconductor device comprising:

a pixel portion comprising a first thin film transistor; and

a driver circuit comprising a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor comprising;

a silicon island over a substrate having an insulating surface, said silicon island comprising a source, a drain, and a channel located between said source and said drain;

a gate electrode provided adjacent to the channel with a gate insulating layer interposed therebetween;

an impurity region having a lower concentration of the impurity than concentrations of the source and the drain provided between the channel and at least one of the source and the drain; and

a layer comprising silicon nitride over the gate electrode and the silicon island, said layer having a portion in contact with the gate insulating layer,

wherein the gate insulating layer extends beyond side edges of the gate electrode to cover the impurity region and an extending portion of the gate insulating layer has a portion which is thinner than a portion of the gate insulating film over the channel, and

wherein the first thin film transistor has a pixel electrode electrically connected to one of the source and the drain.

12. A semiconductor device according to claim 4, wherein the gate insulating film comprises silicon oxide.

20. A semiconductor device according to claim 4, wherein a thickness of the gate insulating film is 500 Å

or less.

28. A semiconductor device according to claim 4, wherein the pixel electrode comprises ITO.

36. A semiconductor device according to claim 4, wherein the gate electrode and the impurity region of the second thin film transistor slightly overlap each other.

42. A semiconductor device according to claim 4, wherein a width of the impurity region of the first thin film transistor is wider than a width of the impurity region of the second thin film transistor.

48. A semiconductor device according to claim 4, wherein the first thin film transistor is an N-channel type thin film transistor.

56. A semiconductor device according to claim 4, wherein the first thin film transistor is a P-channel type thin film transistor.

5. A semiconductor device comprising:

a pixel portion comprising a first thin film transistor; and

a driver circuit comprising a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor comprising;

a silicon island over a substrate having an insulating surface, said silicon island comprising a source, a drain, and a channel located between said source and said drain;

a gate electrode provided adjacent to the channel with a gate insulating layer interposed therebetween;

an impurity region having a lower concentration of the impurity than concentrations of the source and the drain provided between the channel and at least one of the source and the drain; and

a layer comprising silicon nitride over the gate electrode and the silicon island, said layer having portions in contact with the gate insulating layer, the source, and drain respectively,

wherein the gate insulating layer extends beyond side edges of the gate electrode to cover the impurity region and an extending portion of the gate insulating layer has a portion which is thinner than a portion of the gate insulating film over the channel, and

wherein the first thin film transistor has a pixel electrode electrically connected to one of the source and the drain.

13. A semiconductor device according to claim 5, wherein the gate insulating film comprises silicon oxide.

21. A semiconductor device according to claim 5, wherein a thickness of the gate insulating film is 500 Å

or less.

29. A semiconductor device according to claim 5, wherein the pixel electrode comprises ITO.

37. A semiconductor device according to claim 5, wherein the gate electrode and the impurity region of the second thin film transistor slightly overlap each other.

43. A semiconductor device according to claim 5, wherein a width of the impurity region of the first thin film transistor is wider than a width of the impurity region of the second thin film transistor.

49. A semiconductor device according to claim 5, wherein the first thin film transistor is an N-channel type thin film transistor.

57. A semiconductor device according to claim 5, wherein the first thin film transistor is a P-channel type thin film transistor.

6. A semiconductor device comprising:

a pixel portion comprising a first thin film transistor; and

a driver circuit comprising a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor comprising;

a silicon island over a substrate having an insulating surface, said silicon island comprising a source, a drain, and a channel located between said source and said drain;

a gate electrode provided adjacent to the channel with a gate insulating layer interposed therebetween;

an impurity region having a lower concentration of the impurity than concentrations of the source and the drain provided between the channel and at least one of the source and the drain; and

a layer comprising silicon nitride over the gate electrode and the silicon island, said layer having a portion in contact with the gate insulating layer,

wherein the gate insulating layer extends beyond side edges of the gate electrode to cover the source and the drain and an extending portion of the gate insulating layer has a portion which is thinner than a portion of the gate insulating film over the channel, and

wherein the first thin film transistor has a pixel electrode electrically connected to one of the source and the drain.

14. A semiconductor device according to claim 6, wherein the gate insulating film comprises silicon oxide.

22. A semiconductor device according to claim 6, wherein a thickness of the gate insulating film is 500 Å

or less.

30. A semiconductor device according to claim 6, wherein the pixel electrode comprises ITO.

38. A semiconductor device according to claim 6, wherein the gate electrode and the impurity region of the second thin film transistor slightly overlap each other.

44. A semiconductor device according to claim 6, wherein a width of the impurity region of the first thin film transistor is wider than a width of the impurity region of the second thin film transistor.

50. A semiconductor device according to claim 6, wherein the first thin film transistor is an N-channel type thin film transistor.

58. A semiconductor device according to claim 6, wherein the first thin film transistor is a P-channel type thin film transistor.

7. A semiconductor device comprising:

a pixel portion comprising a first thin film transistor; and

a driver circuit comprising a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor comprising;

a silicon island over a substrate having an insulating surface, said silicon island comprising a source, a drain, and a channel located between said source and said drain;

a gate electrode provided adjacent to the channel with a gate insulating layer interposed therebetween; and

a layer comprising silicon nitride over the gate electrode and the silicon island, said layer having a portion in contact with the gate insulating layer,

wherein the gate insulating layer covers the channel, source, and the drain, and

wherein the gate insulating layer has a first portion over the channel and a second portion over at least one of the source and the drain and a thickness of the second portion is thinner than a thickness of the first portion, and

wherein the first thin film transistor has a pixel electrode electrically connected to one of the source and the drain.

15. A semiconductor device according to claim 7, wherein the gate insulating film comprises silicon oxide.

23. A semiconductor device according to claim 7, wherein a thickness of the gate insulating film is 500 Å

or less.

31. A semiconductor device according to claim 7, wherein the pixel electrode comprises ITO.

51. A semiconductor device according to claim 7, wherein the first thin film transistor is an N-channel type thin film transistor.

59. A semiconductor device according to claim 7, wherein the first thin film transistor is a P-channel type thin film transistor.

8. A semiconductor device comprising:

a pixel portion comprising a first thin film transistor; and

a driver circuit comprising a second thin film transistor,

wherein each of the first thin film transistor and the second thin film transistor comprising;

a silicon island over a substrate having an insulating surface, said silicon island comprising a source, a drain, and a channel located between said source and said drain;

a gate electrode provided adjacent to the channel with a gate insulating layer interposed therebetween; and

a layer comprising silicon nitride over the gate electrode and the silicon island, said layer having a portion in contact with the gate insulating layer,

wherein the gate insulating layer extends beyond side edges of the gate electrode to cover the source and the drain and an extending portion of the gate insulating layer has a portion which is thinner than a portion of the gate insulating film over the channel, and

wherein the first thin film transistor has a pixel electrode electrically connected to one of the source and the drain.

16. A semiconductor device according to claim 8, wherein the gate insulating film comprises silicon oxide.

24. A semiconductor device according to claim 8, wherein a thickness of the gate insulating film is 500 Å

or less.

32. A semiconductor device according to claim 8, wherein the pixel electrode comprises ITO.

52. A semiconductor device according to claim 8, wherein the first thin film transistor is an N-channel type thin film transistor.

60. A semiconductor device according to claim 8, wherein the first thin film transistor is a P-channel type thin film transistor.