Differential amplifiers

• US 20070096814A1
• Filed: 11/01/2005
• Published: 05/03/2007
• Est. Priority Date: 11/01/2005
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chiu, Chinq-Shiun
• Granted Patent: US 7,248,116 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2203/45028 the differential amplifier amplifying transistors are folded cascode coupled transistors
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence

Abstract

Differential amplifiers comprise a differential input stage, first, second, third, and fourth fixed current sources, a first resistive element, and a current-folding element. Due to topology thereof, the differential amplifier converts the difference between the input voltages to the voltage difference between the source voltages of the transistors in the differential pair, and a current is induced through the first resistive element, thereby generating two currents. The current-folding element folds the two currents to generate output voltages.

Claims

1. A differential amplifier, comprising:

a differential input stage comprising a first transistor coupled between a first node and a second node, and a second transistor coupled between a third node and a fourth node, wherein control terminals of the first and second transistors receive an input signal;

first, second, third, and fourth fixed current sources coupled between the first node and a first voltage source, between the third node and the first voltage source, between the second node and a second voltage source, and between the fourth node and the second voltage source respectively;

a first resistive element coupled between the second node and the fourth node; and

a current-folding element outputting an output signal and comprising;

a third transistor comprising a first terminal coupled to the first voltage source, a second terminal coupled to the second node and a control terminal coupled to the first node;

a fourth transistor comprising a first terminal coupled to the first voltage source, a second terminal coupled to the fourth node and a control terminal coupled to the third node.

a fifth transistor comprising a first terminal coupled to the first voltage source, a second terminal coupled to a fifth node and a control terminal coupled to the first node; and

a sixth transistor comprising a first terminal coupled to the first voltage source, a second terminal coupled to a sixth node and a control terminal coupled to the third node.

2. The differential amplifier as claimed in claim 1, further comprising a second resistive element coupled between the fifth node, the sixth node and the second voltage source.

3. The differential amplifier as claimed in claim 1, wherein the first to sixth transistors are MOS transistors.

4. The differential amplifier as claimed in claim 1, wherein the first and second transistors are NMOS transistors, and the third to sixth transistors are PMOS transistors.

5. The differential amplifier as claimed in claim 1, wherein the first to sixth transistors are BJT transistors.

6. The differential amplifier as claimed in claim 1, wherein the fifth and sixth transistors comprise a predetermined size exceeding that of the third and fourth transistors, and gain of differential amplifier is adjusted by modifying a size ratio between the fifth transistor and the third transistor.

7. The differential amplifier as claimed in claim 1, wherein the fifth and sixth transistors each comprise a first predetermined number of fingers, the third and fourth transistors each comprise a second predetermined number of fingers, and gain of differential amplifier is adjusted by modifying the first and second predetermined numbers of fingers.

8. The differential amplifier as claimed in claim 2, wherein the first and second resistive elements comprise variable resistors.

9. The differential amplifier as claimed in claim 2, wherein a first voltage difference is generated between the second node and the fourth node by the input stage according to the input signal, generating a first current through the first resistive element.

10. The differential amplifier as claimed in claim 9, wherein a second voltage difference is generated between the first node and the third node according to the first current, such that a second current is generated by the fifth and sixth transistors to the second resistive element to generate the output signal.

11. A semiconductor circuit, comprising:

a differential input stage comprising a first transistor coupled between a first node and a second node, and a second transistor coupled between a third node and a fourth node, wherein control terminals of the first and second transistors receive an input signal;

first, second, third, and fourth fixed current sources coupled between the first node and a first voltage source, between the third node and the first voltage source, between the second node and a second voltage source, and between the fourth node and the second voltage source respectively;

a first resistive element coupled between the second node and the fourth node; and

a current-folding element outputting an output signal and comprising;

a third transistor comprising a first terminal coupled to the first voltage source, a second terminal coupled to the second node and a control terminal coupled to the first node;

a fourth transistor comprising a first terminal coupled to the first voltage source, a second terminal coupled to the fourth node and a control terminal coupled to the third node;

a fifth transistor comprising a first terminal coupled to the first voltage source, a second terminal coupled to a fifth node and a control terminal coupled to the first node; and

a sixth transistor comprising a first terminal coupled to the first voltage source, a second terminal coupled to a sixth node and a control terminal coupled to the third node, wherein the third to sixth transistors are substantially the same size.

12. The semiconductor circuit as claimed in claim 11, wherein the semiconductor circuit is a buffer circuit.

13. The semiconductor circuit as claimed in claim 11, further comprising a second resistive element coupled between the fifth node, the sixth node, and the second voltage source.

14. The semiconductor circuit as claimed in claim 11, wherein the first to sixth transistors are MOS transistors.

15. The semiconductor circuit as claimed in claim 11, wherein the first and second transistors are NMOS transistors, and the third to sixth transistors are PMOS transistors.

16. The semiconductor circuit as claimed in claim 11, wherein the first to sixth transistors are BJT transistors.

17. The semiconductor circuit as claimed in claim 13, wherein the first and second resistive elements comprise variable resistors.

18. The semiconductor circuit as claimed in claim 13, wherein a first voltage difference is generated between the second node and the fourth node by the input stage according to the input signal, generating a first current through the first resistive element.

19. The semiconductor circuit as claimed in claim 18, wherein a second voltage difference is generated between the first node and the third node according to the first current, such that a second current is generated by the fifth and sixth transistors to the second resistive element to generate the output signal.