Data driver and organic light emitting display device using the same

• US 20070096966A1
• Filed: 10/05/2006
• Published: 05/03/2007
• Est. Priority Date: 11/03/2005
• Status: Abandoned Application

• Current Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Park, Yong, Kim, Do
• Application Number:
  US11/544,131
• Publication Number:
  US 20070096966A1
• Time in Patent Office: Days
• US Class Current: 341/144
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0294 Details of sampling or holding circuits arranged for use in a driver for data electrodes
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes

Abstract

A data driver and an organic light emitting display device using the same, in which power consumption and a layout area thereof are reduced. The data driver includes: a shift registering part adapted to supply sampling signals; a sampling latching part including sampling latches adapted to store data in response to the sampling signals; and a holding latching part including holding latches adapted to receive the data stored in the sampling latches in response to an externally supplied source output enable signal. Each of the sampling latches includes sampling bit storages. Each of the sampling bit storages includes: a first input unit adapted to receive a certain bit of the data; a first capacitor adapted to store voltage corresponding to a logic signal of the certain bit supplied from the first input unit; and a first inverter adapted to inverse the logic signal stored in the first capacitor.

Claims

1. A data driver comprising:

a shift registering part adapted to supply sampling signals;

a sampling latching part comprising a plurality of sampling latches adapted to store data in response to the sampling signals; and

a holding latching part comprising a plurality of holding latches adapted to receive the data stored in the sampling latches in response to an externally supplied source output enable signal,

wherein each of the sampling latches comprises a plurality of sampling bit storages, each of the sampling bit storages comprising;

a first input unit adapted to receive a certain bit of the data;

a first capacitor adapted to store voltage corresponding to a logic signal of the certain bit supplied from the first input unit; and

a first inverter adapted to inverse the logic signal stored in the first capacitor.

2. The data driver according to claim 1, wherein the sampling bit storages comprise k sampling bit storages adapted to store data of k bits, and wherein k is a natural number.

3. The data driver according to claim 1, wherein the first input unit comprises:

a first transistor adapted to turn on when the sampling signal is supplied and to supply the certain bit to the first capacitor; and

a second transistor adapted to turn on when an initialization signal is supplied from an external source and to supply a certain voltage to initialize the first capacitor.

4. The data driver according to claim 1, wherein the first input unit comprises a first transistor and a second transistor, and wherein the first transistor and the second transistor are connected in a transmission gate form and supply the certain bit to the first capacitor when the sampling signal and an inversed sampling signal are supplied.

5. The data driver according to claim 1, wherein each of the holding latches comprises a plurality of holding bit storages adapted to store the data supplied from the sampling bit storages.

6. The data driver according to claim 5, wherein the holding bit storages comprises k holding bit storages adapted to store data of k bits, and wherein k is a natural number.

7. The data driver according to claim 5, wherein each of the holding bit storages comprises:

a second input unit adapted to receive the certain bit from the sampling bit storage connected thereto;

a second capacitor adapted to store voltage corresponding to the logic signal of the certain bit supplied from the second input unit; and

a second inverter adapted to inverse the logic signal stored in the second capacitor.

8. The data driver according to claim 7, wherein the second input unit comprises a first transistor and a second transistor, and wherein the first transistor and the second transistor are connected in a transmission gate form and supply the certain bit to the second capacitor when the source output enable signal and an inversed source output enable signal are input.

9. The data driver according to claim 1, further comprising:

a digital-analog converter adapted to receive the data stored in the holding latching part and to generate a data signal corresponding to a digital value of the received data; and

a buffering part adapted to supply the data signal to data lines.

10. The data driver according to claim 9, further comprising a level shifter provided between the digital-analog converter and the holding latching part, and adapted to boost up a voltage level of the data supplied from the holding latching part to the digital-analog converter.

11. An organic light emitting display device comprising:

a scan driver adapted to drive scan lines;

a data driver adapted to supply a data signal to data lines and comprising a plurality of sampling bit storages and a plurality of holding bit storages adapted to store a bit of the data; and

a display region comprising a plurality of pixels connected with the scan lines and the data lines and adapted to emit light corresponding to the data signal, wherein each of the sampling bit storages comprises;

a first input unit adapted to receive a certain bit of the data signal;

a first capacitor adapted to store voltage corresponding to a logic signal of the certain bit supplied from the first input unit; and

a first inverter adapted to inverse the logic signal stored in the first capacitor.

12. The organic light emitting display device according to claim 11, wherein the first input unit comprises:

a first transistor adapted to turn on when a sampling signal is supplied from a shift register provided in the data driver and to supply the certain bit to the first capacitor; and

a second transistor adapted to turn on when an initialization signal is supplied from an external source and to supply a certain voltage to initialize the first capacitor.

13. The organic light emitting display device according to claim 11, wherein the first input unit comprises a first transistor and a second transistor, and wherein the first transistor and the second transistor are connected in a transmission gate form and supply the certain bit to the first capacitor when a sampling signal and an inversed sampling signal are supplied from a shift register provided in the data driver.

14. The organic light emitting display device according to claim 11, wherein each of the holding bit storages comprises:

a second input unit adapted to receive the certain bit from the sampling bit storage connected thereto;

a second capacitor adapted to store voltage corresponding to a logic signal of the certain bit supplied from the second input unit; and

a second inverter adapted to inverse the logic signal stored in the second capacitor.

15. The organic light emitting display device according to claim 14, wherein the second input unit comprises a first transistor and a second transistor which are connected in a transmission gate form and supply the certain bit to the second. capacitor when a source output enable signal and an inversed source output enable signal are input from an external source.

16. The organic light emitting display device according to claim 11, wherein the data driver comprises:

a shift register adapted to supply sampling signals in sequence;

a plurality of sampling latches comprising k sampling bit storages adapted to store data of k bits when the sampling signals are supplied, wherein k is a natural number; and

a plurality of holding latches comprising k holding bit storages adapted to store the data in response to an externally supplied source output enable signal; and

a digital-analog converter adapted to receive the data stored in the holding latches and to generate a data signal corresponding to a digital value of the received data.

17. The organic light emitting display device according to claim 17, wherein the data driver comprises:

a level shifter provided between the digital-analog converter and the holding latches and adapted to boost up a voltage level of the data supplied from the holding latches to the digital-analog converter; and

a buffering part adapted to supply the data signal to the data lines.

18. A data driver comprising:

a shift registering part adapted to supply sampling signals;

a sampling latching part comprising a plurality of sampling latches adapted to store data in response to the sampling signals; and

a holding latching part comprising a plurality of holding latches adapted to receive the data stored in the sampling latches in response to an externally supplied source output enable signal,

wherein each of the holding latches comprises a plurality of holding bit storages, each of the holding bit storages comprising;

a first input unit adapted to receive a certain bit of the data;

a first capacitor adapted to store voltage corresponding to a logic signal of the certain bit supplied from the first input unit; and

a first inverter adapted to inverse the logic signal stored in the first capacitor.

19. The data driver according to claim 18, wherein each of the sampling latches comprises a plurality of sampling bit storages adapted to supply the data to the holding bit storages.

20. The data driver according to claim 18, wherein the first input unit comprises a first transistor and a second transistor, and wherein the first transistor and the second transistor are connected in a transmission gate form and supply the certain bit to the second capacitor when the source output enable signal and an inversed source output enable signal are input.