CMOS image sensor apparatus with on-chip real-time pipelined JPEG compression module

• US 20070097239A1
• Filed: 09/21/2006
• Published: 05/03/2007
• Est. Priority Date: 08/27/2002
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Subbotin, Igor, Kaplinsky, Michael, Lin, Xiuhong
• Application Number:
  US11/524,534
• Publication Number:
  US 20070097239A1
• Time in Patent Office: Days
• US Class Current: 348/282
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

A CMOS imager in which a CMOS image sensor, a color image processing module and an image compression module are all provided on a single die. Both the color image processing module and the image compression module incorporate pipelined architectures to process the image data at a video rate in a massively parallel fashion.

Claims

1-25. -25. (canceled)

26. A CMOS imaging device integrated on a single chip, comprising:

a CMOS image sensor;

a color image processing module;

an image storage module coupled to said color image processing module; and

an image compression module coupled to said image storage module,

wherein said image compression module has a pipelined architecture for processing image data in a parallel fashion at video rates without requiring a full frame memory buffer,

wherein said image compression module implements JPEG compression at video rates, and

wherein said image storage module comprises a plurality of line buffers at a front end of the compression module to allow two-dimensional processing.

27. A CMOS imaging device integrated on a single chip, comprising:

a CMOS image sensor;

a color image processing module;

an image storage module coupled to said color image processing module; and

an image compression module coupled to said image storage module,

wherein said image compression module has a pipelined architecture for processing image data in a parallel fashion at video rates without requiring a full frame memory buffer,

wherein said image compression module implements JPEG compression at video rates, and

wherein said image storage module uses an SRAM addressing scheme to allow maximum utilization rate of memory, comprising reading and writing to one SRAM at the same rate without overwriting.

28. The CMOS imaging device of claim 27, wherein an address calculation formula is used in SRAM addressing.

29. A CMOS imaging device integrated on a single chip, comprising:

a CMOS image sensor;

a color image processing module;

an image storage module coupled to said color image processing module;

an image compression module coupled to said image storage module; and

a buffer at the output of the image compression module to allow for periods of fixed-rate data output interspersed with periods of inactivity,

wherein said image compression module has a pipelined architecture for processing image data in a parallel fashion at video rates without requiring a full frame memory buffer, and

wherein said image compression module implements JPEG compression at video rates.

30. The CMOS imager device of claim 29, wherein the output buffer is a dual-ported memory provided with a pointer control block, such that the buffer functions as a FIFO memory.

31. The CMOS imager device of claim 30, wherein the pointer control block allows for the storage of the output of the encoder as soon as it becomes available, while allowing independent retrieval of data based on external requests.

32. The CMOS imager device of claim 30, further comprising a FIFO &

Register &

CPU control block to enable register access and FIFO access via a single system data/memory bus.

33. The CMOS imager device of claim 32, wherein the FIFO &

Register &

CPU control block generates an INT signal reflecting the current state of the FIFO.

34. The CMOS imager device of claim 30, wherein the FIFO pointer control block generates half-full and almost-empty/full flags reflecting the state of the content of the FIFO memory.

35. The CMOS imager device of claim 30, wherein the FIFO outputs are connected directly to a data/memory bus of a system, allowing for access to the system to be performed over standard system communication channels.

36. The CMOS imager device of claim 35, wherein access to registers and control functions of the imager system is also performed over said data/memory bus.

37. The CMOS imager device of claim 32, wherein control signals are provided to distinguish between image access, register write, and register read traffic over the output pins.

38. The CMOS imager device of claim 30, further comprising circuitry for multiplexing compressed and uncompressed video to an input port of the FIFO memory.

39. A process for processing image data from a CMOS imager device, comprising the steps of:

converting an image to image data using a CMOS image sensor;

color image processing said image data from a first format which is native to a CMOS imager to a second format more suitable for image compression;

storing said processed image data in a memory; and

compressing said stored image data using a processing module having a pipelined architecture for processing image data in a parallel fashion at video rates without requiring a full frame memory buffer,

wherein said step of compressing the image comprises JPEG compression at video rates, and

wherein said step of storing said processed image data in a memory comprises using an SRAM addressing scheme to allow maximum utilization rate of memory, said SRAM addressing scheme comprising reading and writing to one SRAM at the same rate without overwriting.