Fabrication of a high fill ratio silicon spatial light modulator

• US 20070097485A1
• Filed: 06/05/2006
• Published: 05/03/2007
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Original Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Inventors: Payne, Justin, Wang, Yuxiang, Yang, Xiao, Wang, Ye, Ji, Wook, Woo, Howard
• Granted Patent: US 7,675,670 B2
• Time in Patent Office: Days
• US Class Current: 359/290
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means

Abstract

A method for forming an optical deflection device includes providing a semiconductor substrate comprising an upper surface region and a plurality of drive devices within one or more portions of the semiconductor substrate. The upper surface region includes one or more patterned structure regions and at least one open region to expose a portion of the upper surface region to form a resulting surface region. The method also includes forming a planarizing material overlying the resulting surface region to fill the at least one open region and cause formation of an upper planarized layer using the fill material. The method further includes forming a thickness of silicon material at a temperature of less than 300 ° C. to maintain a state of the planarizing material.

Claims

1. A method for forming an optical deflection device, the method comprising:

providing a semiconductor substrate comprising an upper surface region and a plurality of drive devices within one or more portions of the semiconductor substrate, the upper surface region including one or more patterned structure regions and at least one open region to expose a portion of the upper surface region to form a resulting surface region;

forming a planarizing material overlying the resulting surface region to fill the at least one open region and cause formation of an upper planarized layer using the fill material; and

forming a thickness of silicon material at a temperature of less than 300°

C. to maintain a state of the planarizing material.

2. The method of claim 1 wherein the silicon material is substantially amorphous silicon.

3. The method of claim 2 wherein forming a thickness of silicon material is performed at a temperature of less than 200°

C.

4. The method of claim 3 wherein forming a thickness of silicon material is performed at a temperature of less than 100°

C.

5. The method of claim 2 wherein forming a thickness of silicon material comprises a physical vapor deposition process.

6. The method of claim 1 wherein the planarizing material comprises photoresist.

7. The method of claim 6 wherein forming a planarizing material comprises:

depositing a photoresist layer;

partially exposing the photoresist layer; and

developing the partially exposed photoresist layer.

8. The method of claim 1 wherein the state of the planarizing material comprises a cross-sectional shape of the planarizing material.

9. The method of claim 1 further comprising patterning the thickness of silicon material to form a mirror structure.

10. The method of claim 1 further comprising removing the planarizing material to release the mirror structure.

11. The method of claim 1 further comprising removing a portion of the planarizing material to expose a hinge device providing a base region for the thickness of silicon material.

12. A method of fabricating an optical deflection device, the method comprising:

providing a substrate;

forming a planarized dielectric layer over the substrate;

forming a cavity in the planarized dielectric layer;

performing a layer transfer process to bond a single crystal silicon layer to the planarized dielectric layer;

forming a plurality of vias passing through the single crystal silicon layer and the planarized dielectric layer;

forming a plurality of electrical connections passing through the plurality of vias;

forming a hinge coupled to the substrate;

forming a planarized material layer coupled to the hinge;

forming a cavity in the planarized material layer;

forming a mirror structure filling at least a portion of the cavity; and

releasing the mirror structure.

13. The method of claim 12 further comprising forming a mirror coating layer coupled to the mirror structure.

14. The method of claim 12 wherein the mirror structure comprises:

a mirror post; and

a mirror plate coupled to the mirror post and overlying the substrate.

15. The method of claim 12 wherein the mirror structure comprises a silicon mirror structure.

16. The method of claim 12 wherein the substrate comprises a number of electrodes and associated electrode drivers.

17. The method of claim 12 wherein forming a planarized dielectric layer comprises:

depositing an oxide layer using an HDP process; and

planarizing the deposited oxide layer using a CMP process.

18. The method of claim 17 wherein depositing an oxide layer is performed at a temperature less than a temperature associated with a state change of an underlying material.

19. The method of claim 18 wherein the temperature is less than an aluminum reflow temperature.

20. The method of claim 19 wherein the aluminum reflow temperature is about 450°

C.

21. The method of claim 18 wherein depositing an oxide layer is performed at a temperature less than a glass transition temperature of photoresist.

22. The method of claim 21 wherein the glass transition temperature of photoresist is about 150°

C.

23. The method of claim 12 wherein the layer transfer process comprises a substrate bonding process.

24. The method of claim 23 wherein the substrate bonding process provides a covalent bond between the planarized dielectric layer and the single crystal silicon layer.

25. The method of claim 12 wherein the plurality of vias comprises:

a first set of vias providing an electrical conduction path to a bias line; and

a second set of vias providing an electrical conduction path to a bias grid.

26. The method of claim 12 wherein the plurality of electrical connections comprise via plugs.

27. The method of claim 12 wherein the plurality of electrical connections comprise a conformal metal layer.

28. The method of claim 27 wherein the conformal metal layer comprises a composite Ti/Al layer.

29. The method of claim 12 further comprising forming an upper electrode by patterning and removing a portion of the single crystal silicon layer.

30. The method of claim 12 wherein forming the mirror structure comprises depositing and planarizing an amorphous silicon layer.

31. The method of claim 30 wherein depositing and planarizing an amorphous silicon layer is performed at a temperature of less than 150°

C.

32. The method of claim 12 wherein the mirror structure comprises a polysilicon layer.

33. The method of claim 12 wherein the mirror structure comprises a silicon/metal alloy.

34. The method of claim 33 wherein silicon/metal alloy comprises a silicon/Al alloy.

35. The method of claim 12 wherein the mirror coating layer comprises a composite Ti/Al layer.

36. The method of claim 12 wherein releasing the mirror structure comprises removing the material layer using an O₂ plasma ashing process.

37. The method of claim 12 further comprising fabricating a mirror electrode on a surface of the silicon mirror layer.

38. The method of claim 37 wherein the surface of the silicon mirror layer is a bottom surface opposing the first substrate.

39. A method for forming a planarized layer, the method comprising:

providing a semiconductor substrate comprising an upper surface region and a plurality of drive devices within one or more portions of the semiconductor substrate, the upper surface region including one or more patterned structure regions and at least one open region to expose a portion of the upper surface region to form a resulting surface region;

dispensing a fill material having a fluid characteristic overlying the resulting surface region to fill the at least one open region and cause formation of an upper planarized layer using the fill material.

40. The method of claim 39 wherein the resulting surface region is characterized by a width to depth aspect ratio of less than one.

41. The method of claim 39 wherein the fill material comprises an organic material.

42. The method of claim 41 wherein the fill material comprises photoresist.

43. The method of claim 41 wherein the fill material comprises a spin on glass material.

44. The method of claim 39 wherein the fluid characteristic is selected to cause the formation of the upper planarized layer.

45. The method of claim 39 further comprising rotating the substrate about an axis during at least a portion of the dispensing step.

46. The method of claim 39 wherein the at least one open region is characterized by a spatial characteristic, the spatial characteristic being at least as large as the patterned structure region.

47. The method of claim 39 wherein the one or more patterned structure regions comprise at least two electrode structures.

48. The method of claim 39 wherein the upper planarized layer is provided as a fabrication base for a mirror structure.

49. The method of claim 39 wherein dispensing a fill material forms a first resulting thickness having a first planarized surface region and further comprising reducing the first resulting thickness to a second resulting thickness.

50. The method of claim 39 wherein the upper planarized layer is characterized by a peak to valley roughness of less than 50 nm.

51. A method of forming a composite substrate structure, the method comprising:

providing a substrate comprising a plurality of electrode devices;

forming a planarized dielectric layer over the substrate, the planarized dielectric layer defining an upper surface opposing the substrate;

forming a cavity extending from the upper surface of the planarized dielectric layer to a predetermined depth, wherein a cavity volume is defined by a cavity area parallel to the upper surface of the planarized dielectric layer and the predetermined depth;

joining a single crystal silicon layer to the upper surface of the planarized dielectric layer to define a bond area greater than the cavity area.

52. The method of claim 51 wherein the bond area is two times greater than the cavity area.

53. The method of claim 52 wherein the bond area is ten times greater than the cavity area.

54. The method of claim 53 wherein the bond area is 90 times greater than the cavity area.

55. The method of claim 54 wherein the bond area is characterized by a bonded area to a total area of greater than 10%.

56. The method of claim 51 wherein the plurality of electrode devices comprise a plurality of multi-level electrode devices.

57. The method of claim 56 wherein a portion of a first level of the plurality of multi-level electrode devices is covered by the planarized dielectric layer and a portion of a second level of the plurality of multi-level electrode devices is formed from the single crystal silicon layer.

58. The method of claim 51 wherein the planarized dielectric layer comprises an HDP silicon oxide layer.

59. The method of claim 58 wherein the HDP silicon oxide layer is formed at a temperature of less than 200°

C.

60. The method of claim 59 wherein the HDP silicon oxide layer is formed at a temperature of less than 150°

C.

61. The method of claim 51 wherein the planarized dielectric layer is fabricated from a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, poly-silicon, amorphous silicon, and low temperature poly-silicon.

62. The method of claim 51 wherein forming a planarized dielectric layer comprises a CMP process.

63. The method of claim 51 wherein joining a single crystal silicon layer to the upper surface of the planarized dielectric layer comprises performing a substrate bonding process.

64. The method of claim 63 wherein the substrate bonding process comprises a silicon-on-insulator substrate bonding process.

65. The method of claim 63 wherein the substrate bonding process is performed at a temperature less than an aluminum reflow temperature.

66. The method of claim 51 wherein joining a single crystal silicon layer to the upper surface of the planarized dielectric layer comprises:

substrate bonding an SOI substrate to planarized dielectric layer;

removing a first silicon layer; and

removing a buried oxide layer to expose the single crystal silicon layer.

67. The method of claim 51 wherein joining a single crystal silicon layer to the upper surface of the planarized dielectric layer is performed using an alignment process with a tolerance requirement of less than 1 cm.

68. The method of claim 67 wherein joining a single crystal silicon layer to the upper surface of the planarized dielectric layer comprises forming a covalent bond at room temperature.

69. The method of claim 68 wherein joining a single crystal silicon layer to the upper surface of the planarized dielectric layer comprises a plasma activation process and a room temperature covalent bonding process.