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Use of Data Latches in Multi-Phase Programming of Non-Volatile Memories

  • US 20070097744A1
  • Filed: 12/04/2006
  • Published: 05/03/2007
  • Est. Priority Date: 04/01/2005
  • Status: Active Grant
First Claim
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1. A non-volatile memory device, comprising:

  • one or more memory cells each capable of storing N bits of data, where N is greater than or equal to one; and

    read/write circuitry connectable to the memory cells, comprising;

    programming circuitry to apply a monotonically non-decreasing programming waveform to the memory cells;

    bias circuitry to set bias conditions in the memory cells concurrently with the programming waveform being applied to the memory cells, wherein a first set of bias conditions is used during a first programming phase and a second set of bias conditions is used during a second programming phase; and

    one or more sets of latches each associated with a corresponding one of the memory cells to which the read/write circuitry is connected, wherein a first latch of each of said sets of latches governs which of the programming phases is active.

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