Asynchronous first-in first-out cell

• US 20070097771A1
• Filed: 01/12/2006
• Published: 05/03/2007
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: National Chiao Tung University (Government of The Republic of China)
• Original Assignee: National Chiao Tung University (Government of The Republic of China)
• Inventors: Chu, Yeh-Lin, Hwang, Wei
• Granted Patent: US 7,260,008 B2
• Time in Patent Office: Days
• US Class Current: 365/221
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers

Abstract

The present invention discloses an asynchronous first-in-first-out cell, wherein modified Muller C elements are used to reduce the complexity of the circuit of the asynchronous first-in-first-out cell; the asynchronous first-in-first-out cell of the present invention not only can be reusable, but also can apply to a single-supply-voltage system with a single clock frequency or multiple clock frequencies and a multiple-supply-voltage system with a single clock frequency or multiple clock frequencies. Further, when the asynchronous first-in-first-out cell of the present invention is applied to the interface circuit of a dual-supply-voltage 16-point radix-2² GALS-based FFT architecture, considerable power saving and latency reduction can be achieved.

Claims

1. A single-supply-voltage asynchronous first-in-first-out cell, positioned between a first asynchronous wrapper and a second asynchronous wrapper, and comprising:

a data latch, further comprising a register, and responsible for inputting and outputting data;

a full/empty detector, detecting the data access state of said data latch;

a sender'"'"'s handshake controller, coupled to said data latch and said full/empty detector, learning from said full/empty detector that the storage space of said data latch is not full yet, receiving a sender'"'"'s token signal, creating a sender'"'"'s acknowledge signal and sending it to said first asynchronous wrapper; and

a receiver'"'"'s handshake controller, coupled to said data latch and said full/empty detector, learning from said full/empty detector that there is data stored in said data latch, receiving a receiver'"'"'s token signal, creating a receiver'"'"'s acknowledge signal and sending it to said second asynchronous wrapper.

2. The single-supply-voltage asynchronous first-in-first-out cell according to claim 1, wherein the data cannot be stored into said data latch unless said sender'"'"'s handshake controller has received said sender'"'"'s token;

if said data latch has no storage space for said data, said sender'"'"'s acknowledge signal is not sent to said first asynchronous wrapper until said data latch has storage space.

3. The single-supply-voltage asynchronous first-in-first-out cell according to claim 1, wherein the data stored in sad data latch cannot be output unless said receiver'"'"'s handshake controller has received said receiver'"'"'s token;

if the data stored in said data latch has been output, said receiver'"'"'s acknowledge signal is not sent to said second asynchronous wrapper until there is data stored in said data latch.

4. The single-supply-voltage asynchronous first-in-first-out cell according to claim 1, wherein said first asynchronous wrapper further comprises:

a first locally-synchronous module, creating a first enable signal when said first locally-synchronous module is ready to store data into said data latch;

a first handshake generator, receiving said first enable signal, creating a sender'"'"'s request signal and send it to said sender'"'"'s handshake controller, creating a first stretch signal, and receiving said sender'"'"'s acknowledge signal from said sender'"'"'s handshake controller; and

a first plausible clock controller, receiving and processing said first stretch signal, creating a first local clock signal and sending it to said first locally-synchronous module, which then sends data to said data latch.

5. The single-supply-voltage asynchronous first-in-first-out cell according to claim 1, wherein said second asynchronous wrapper further comprises:

a second locally-synchronous module, creating a second enable signal when said second locally-synchronous module is ready to output the data temporarily stored in said data latch;

a second handshake generator, receiving said second enable signal, creating a receiver'"'"'s request signal and send it to said receiver'"'"'s handshake controller, creating a second stretch signal, and receiving said receiver'"'"'s acknowledge signal from said receiver'"'"'s handshake controller; and

a second plausible clock controller, receiving and processing said second stretch signal, creating a second local clock signal and sending it to said second locally-synchronous module, which then receives the data stored in said data latch.

6. The single-supply-voltage asynchronous first-in-first-out cell according to claim 4, wherein said first plausible clock controller can stop or prolong said first stretch signal lest the time that said first stretch signal arrives at said first plausible clock controller be too close to the time that data is processed to transfer to said data latch.

7. The single-supply-voltage asynchronous first-in-first-out cell according to claim 5, wherein said second plausible clock controller can stop or prolong said second stretch signal lest the time that said second stretch signal arrives at said second plausible clock controller be too close to the time that the data stored in said data latch is processed to output.

8. The single-supply-voltage asynchronous first-in-first-out cell according to claim 1, wherein said full/empty detector further comprises:

a first CMOS, receiving said sender'"'"'s acknowledge signal with the P-type transistor of said first CMOS externally coupled to an inverter;

a second CMOS, receiving said receiver'"'"'s acknowledge signal, and positioned between the P-type and N-type transistors of said first CMOS;

an N-type transistor, coupled to between the P-type and N-type transistors of said second CMOS, and functioning as the input terminal of a reset signal when said full/empty detector detects that there is data stored in said data latch; and

a first output terminal, externally coupled to an inverter, positioned between the P-type and N-type transistors of said second CMOS, and functioning as the output terminal of the signals of said full/empty detector.

9. The single-supply-voltage asynchronous first-in-first-out cell according to claim 4, wherein said sender'"'"'s handshake controller further comprises:

a third CMOS, receiving said receiver'"'"'s acknowledge signal, with the N-type transistor thereof externally coupled to an inverter;

a fourth CMOS, receiving the inversion signal of said sender'"'"'s acknowledge signal, and positioned between the P-type and N-type transistors of said third CMOS;

a fifth CMOS, receiving said sender'"'"'s request signal, positioned between the P-type and N-type transistors of said fourth CMOS;

a first P-type transistor, coupled to between the P-type and N-type transistors of said fifth CMOS, and functioning as the input terminal of an inversion signal when said full/empty detector detects that there is data stored in said data latch; and

a second output terminal, externally coupled to an inverter, positioned between the P-type and N-type transistors of said fifth CMOS, and functioning as the output terminal of the signals of said sender'"'"'s handshake controller.

10. The single-supply-voltage asynchronous first-in-first-out cell according to claim 5, wherein said receiver'"'"'s handshake controller further comprises:

a sixth CMOS, receiving the inversion signal of said receiver'"'"'s acknowledge signal;

a seventh CMOS, receiving said receiver'"'"'s request signal, and positioned between the P-type and N-type transistors of said sixth CMOS;

a second P-type transistor, coupled to between the P-type and N-type transistors of said seventh CMOS, and functioning as the input terminal of an inversion signal when said full/empty detector detects that there is no data stored in said data latch; and

a third output terminal, externally coupled to an inverter, positioned between the P-type and N-type transistors of said seventh CMOS, and functioning as the output terminal of the signals of said receiver'"'"'s handshake controller.

11. The single-supply-voltage asynchronous first-in-first-out cell according to claim 9, wherein one control signal of said sender'"'"'s handshake controller is a signal output by said receiver'"'"'s handshake controller lest there should be a data transparent problem from the input data to the output data.

12. A dual-supply-voltage asynchronous first-in-first-out cell, positioned between a first asynchronous wrapper and a second asynchronous wrapper, wherein said first asynchronous wrapper is externally coupled to a first supply voltage, and said second asynchronous wrapper is externally coupled to a second supply voltage, and said second supply voltage is greater than said first supply voltage, and comprising:

a data latch, responsible for data input/output, and further comprising a level converter flip-flop, which has flip-flop and level conversion functions;

a full/empty detector, used to detect the data access state of said data latch;

a sender'"'"'s handshake controller, coupled to said data latch and said full/empty detector, learning from said full/empty detector that the storage space of said data latch is not full yet, receiving a sender'"'"'s token signal, creating a sender'"'"'s acknowledge signal and sending it to said first asynchronous wrapper;

a receiver'"'"'s handshake controller, coupled to said data latch and said full/empty detector, learning from said full/empty detector that there is data stored in said data latch, receiving a receiver'"'"'s token signal, creating a receiver'"'"'s acknowledge signal and sending it to said second asynchronous wrapper; and

an asynchronous level converter, coupled to said receiver'"'"'s handshake controller and said full/empty detector, and converting said first supply voltage into said second supply voltage.

13. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 12, wherein the data cannot be stored into said data latch unless said sender'"'"'s handshake controller has received said sender'"'"'s token;

if said data latch has no storage space for said data, said sender'"'"'s acknowledge signal is not sent to said first asynchronous wrapper until said data latch has storage space.

14. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 12, wherein the data stored in said data latch cannot be output unless said receiver'"'"'s handshake controller has received said receiver'"'"'s token;

if the data stored in said data latch has been output, said receiver'"'"'s acknowledge signal is not sent to said second asynchronous wrapper until there is data stored in said data latch.

15. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 12, wherein said first asynchronous wrapper further comprises:

a first locally-synchronous module, creating a first enable signal when said first locally-synchronous module is ready to store data into said data latch;

a first handshake generator, receiving said first enable signal, creating a sender'"'"'s request signal and send it to said sender'"'"'s handshake controller, creating a first stretch signal, and receiving said sender'"'"'s acknowledge signal from said sender'"'"'s handshake controller; and

a first plausible clock controller, receiving and processing said first stretch signal, creating a first local clock signal and sending it to said first locally-synchronous module, which then sends data to said data latch.

16. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 12, wherein said second asynchronous wrapper further comprises:

a second locally-synchronous module, creating a second enable signal when said second locally-synchronous module is ready to output the data temporarily stored in said data latch;

a second handshake generator, receiving said second enable signal, creating a receiver'"'"'s request signal and send it to said receiver'"'"'s handshake controller, creating a second stretch signal, and receiving said receiver'"'"'s acknowledge signal from said receiver'"'"'s handshake controller; and

a second plausible clock controller, receiving and processing said second stretch signal, creating a second local clock signal and sending it to said second locally-synchronous module, which then receives the data stored in said data latch.

17. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 15, wherein said first plausible clock controller can stop or prolong said first stretch signal lest the time that said first stretch signal arrives at said first plausible clock controller be too close to the time that data is processed to transfer to said data latch.

18. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 16, wherein said second plausible clock controller can stop or prolong said second stretch signal lest the time that said second stretch signal arrives at said second plausible clock controller be too close to the time that the data stored in said data latch is processed to output.

19. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 12, wherein said full/empty detector further comprises:

a first CMOS, receiving said sender'"'"'s acknowledge signal with the P-type transistor of said first CMOS externally coupled to an inverter;

a second CMOS, receiving said receiver'"'"'s acknowledge signal, and positioned between the P-type and N-type transistors of said first CMOS;

an N-type transistor, coupled to between the P-type and N-type transistors of said second CMOS, and functioning as the input terminal of a reset signal when said full/empty detector detects that there is data stored in said data latch; and

a first output terminal, externally coupled to an inverter, positioned at said second CMOS, and functioning as the output terminal of the signals of said full/empty detector.

20. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 15, wherein said sender'"'"'s handshake controller further comprises:

a third CMOS, receiving said receiver'"'"'s acknowledge signal, with the N-type transistor thereof externally coupled to an inverter;

a fourth CMOS, receiving the inversion signal of said sender'"'"'s acknowledge signal, and positioned between the P-type and N-type transistors of said third CMOS;

a fifth CMOS, receiving said sender'"'"'s request signal, positioned between the P-type and N-type transistors of said fourth CMOS;

a first P-type transistor, coupled to between the P-type and N-type transistors of said fifth CMOS, and functioning as the input terminal of an inversion signal when said full/empty detector detects that there is data stored in said data latch; and

a second output terminal, externally coupled to an inverter, positioned between the P-type and N-type transistors of said fifth CMOS, and functioning as the output terminal of the signals of said sender'"'"'s handshake controller.

21. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 16, wherein said receiver'"'"'s handshake controller further comprises:

a sixth CMOS, receiving the inversion signal of said receiver'"'"'s request signal;

a seventh CMOS, receiving said receiver'"'"'s request signal, and positioned between the P-type and N-type transistors of said sixth CMOS;

a second P-type transistor, coupled to between the P-type and N-type transistors of said seventh CMOS, and functioning as the input terminal of an inversion signal when said full/empty detector detects that there is no data stored in said data latch; and

a third output terminal, externally coupled to an inverter, positioned between the P-type and N-type transistors of said seventh CMOS, and functioning as the output terminal of the signals of said receiver'"'"'s handshake controller.

22. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 20, wherein one control signal of said sender'"'"'s handshake controller is a signal output by said receiver'"'"'s handshake controller, which can prevent the data transparent problem occurring from the input data to the output data.

23. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 12, wherein said level converter flip-flop adopts a pulsed flip-flop, and when said level converter flip-flop samples said sender'"'"'s acknowledge signals, it is equivalent to a pulse.

24. The dual-supply-voltage asynchronous first-in-first-out cell according to claim 12, wherein said asynchronous level converter can avoid extra power consumption when P-type transistors are not totally turned off.