Methods and arrangements to model an asynchronous interface

• US 20070098020A1
• Filed: 10/27/2005
• Published: 05/03/2007
• Est. Priority Date: 10/27/2005
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ja, Yee, Nelson, Bradley
• Application Number:
  US11/260,557
• Publication Number:
  US 20070098020A1
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

Methods and arrangements to model an asynchronous interface are disclosed. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or time-constrained, asynchronous interface and employ the skew pattern in data transfers during a time interval in which the asynchronous interface. Embodiments may then alter the skew pattern in at the expiration of the time interval. In many embodiments, changes to the skew pattern may be substantially non-deterministic. In other embodiments, changes to the skew pattern may follow a heuristic or other dynamic or pre-determined pattern.

Claims

1. A method to model behavior of an asynchronous interface, the method comprising:

generating a first pattern of skews for a number of bit lines of the asynchronous interface;

applying the first pattern of skews to bits associated with the number of bit lines during a time interval; and

applying a second pattern of skews to subsequent bits associated with the number of bit lines after the time interval.

2. The method of claim 1, further comprising determining a skew pattern between the number of bit lines based upon comparison between bits of a test pattern and a pattern of received bits.

3. The method of claim 1, further comprising counting clock cycles of the time interval and resetting the time interval upon transmission of a test pattern of bits.

4. The method of claim 1, wherein generating the first pattern comprises generating a selection signal for a multiplexor logic to select a skew for at least one of the bit lines.

5. The method of claim 4, wherein generating the first pattern comprises selecting the skew from a set of skews via the multiplexor logic based upon the selection signal, wherein a probability of selection of the skew from the set of skews is predetermined.

6. The method of claim 1, wherein applying the first pattern comprises applying the first pattern prior to transmission of data across the asynchronous interface.

7. The method of claim 1, wherein applying the first pattern comprises applying the first pattern upon receipt of data at a receiver from the asynchronous interface.

8. The method of claim 1, wherein applying the second pattern of skews comprises generating the second pattern of skews.

9. The method of claim 7, wherein generating the second pattern of skews comprises selecting skews for each of the number of bit lines in a substantially non-deterministic manner.

10. A system to model behavior of an asynchronous interface, the system comprising:

a delay applicator to apply skews to bits crossing the asynchronous interface via a number of bit lines; and

a delay generator to generate a first pattern of the skews for the number of bit lines during a time interval and to generate a second pattern of skews for subsequent bits crossing the asynchronous interface via the number of bit lines after the time interval.

11. The system of claim 10, further comprising a synch counter to count clock cycles of the time interval to indicate an end of the time interval and to restart the time interval upon transmission of test pattern data.

12. The system of claim 10, wherein the delay applicator comprises delay logic to apply the skews prior to transmission of the bits across the asynchronous interface.

13. The system of claim 10, wherein the delay applicator comprises delay logic to apply the skews after receipt of the bits from the bit lines.

14. The system of claim 11, wherein the delay generator couples with the synch counter to generate the second pattern of skews upon expiration of the time interval, wherein the second pattern of skews is substantially non-deterministic.

15. The system of claim 10, wherein the delay generator comprises random logic to generate a selection signal for a multiplexor logic to select from the skews applied to the bits crossing the asynchronous interface for at least one of the bit lines.

16. The system of claim 15, wherein the delay generator comprises the multiplexor logic to select from the skews applied to the bits crossing the asynchronous interface based upon the selection signal, wherein a probability of selection of a skew from the skews is predetermined.

17. The system of claim 15, wherein the multiplexor logic is adapted to independently select a skew from the skews for each of the number of bit lines.

18. A machine-accessible medium containing instructions to model behavior of an asynchronous interface, which when the instructions are executed by a machine, cause said machine to perform operations, comprising:

generating a first pattern of skews for a number of bit lines of the asynchronous interface;

applying the first pattern of skews to bits associated with the number of bit lines during a time interval; and

applying a second pattern of skews to subsequent bits associated with the number of bit lines after the time interval.

19. The machine-accessible medium of claim 18, wherein the operations further comprise counting clock cycles of the time interval and resetting the time interval upon transmission of a test pattern of bits.

20. The machine-accessible medium of claim 18, wherein the operations further comprise determining a skew pattern between the number of bit lines based upon comparison between bits of a test pattern and a pattern of received bits.