Method and apparatus for discrete power synthesis of multicarrier signals with constant envelope power amplifiers

• US 20070098109A1
• Filed: 08/06/2004
• Published: 05/03/2007
• Est. Priority Date: 08/07/2003
• Status: Active Grant

• Current Assignee: Nokia Corporation
• Original Assignee: Nokia Corporation
• Inventors: Kuchi, Kiran, Vadde, Venkatesh
• Granted Patent: US 7,539,269 B2
• Time in Patent Office: Days
• US Class Current: 375/297
• CPC Class Codes: H03F 1/0294 using vector summing of two or more constant amplitude phase-modulated signals
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04L 27/2614 Peak power aspects
• CPC Class Codes: H04W 52/04 TPC

Abstract

A power synthesizer is in several (n) discrete stages, each stage having a discrete amplitude, constant envelope amplifier coupled in series with a continuous phase modulator. Each modulator is actuated simultaneously, but not necessarily to modulate the signal phase similarly. For circuit power combining, the modulators are coupled to inputs of the amplifiers, while the separately modulated and amplified bits are combined prior to being fed to the antenna. For spatial power combining, each modulator is coupled to the input of an amplifier which in turn feeds one of several antennas. Each stage operates on one bit, and each successive n^th stage amplifies the input bit by a factor of a0/2^n-1. Preferably, a discrete amplitude generator converts an (analog) output of an IFFT block to a binary sequence, and each bit is fed to a separate stage. The power synthesizer converts a digital output of the discrete amplitude generator to analog at RF rather than at baseband, rendering a baseband DAC, and a separate upconverter, unnecessary.

Claims

1. A power synthesizer comprising

a plurality of n stages in parallel with one another, wherein n is an integer at least equal to two, each of the n stages comprising:

a modulator and a discrete amplitude amplifier in series with one another,

each n^th discrete amplitude amplifier for applying a gain that is unique as compared to all other of the discrete amplitude amplifiers; and

an actuator for simultaneously switching the n modulators.

2. The power synthesizer of claim 1 wherein each of the n discrete amplifiers comprises a constant envelope amplifier.

3. The power synthesizer of claim 1 wherein each of the n modulators comprises a continuous phase modulator.

4. The power synthesizer of claim 3 wherein each of the n modulators comprises a pulse-amplitude modulator.

5. The power synthesizer of claim 1 further comprising a power combiner having parallel inputs coupled to outputs of the n discrete amplitude amplifiers.

6. The power synthesizer of claim 1, wherein, for each of the n stages, the discrete amplitude amplifier has an input that is directly coupled to an output of the modulator.

7. The power synthesizer of claim 1 further comprising a discrete amplitude generator having parallel outputs coupled to inputs of the n stages, said discrete amplitude generator for converting a real input to parallel binary outputs.

9. The power synthesizer of claim 1, wherein each of the n stages has an output coupled to an input of a separate transmit antenna.

10. The power synthesizer of claim 1 wherein

each of the modulators is coupled to a common actuator;

and

each n^th amplifier is for outputting a signal amplitude a₀/2^n-1, where a₀ is a maximum signal amplitude output by any of said amplifiers,

the power synthesizer further comprising a discrete amplitude generator for converting a real valued input to a first and second parallel binary outputs that are each coupled to an input of the respective first and second modulators.

11. The power synthesizer of claim 1 wherein, in one stage, the discrete amplitude amplifier comprises x FETs each having a drain and a gates, and in another stage, the discrete amplitude amplifier comprises x/2 FETs each having a drain and a gate, wherein x is an integer greater than two, wherein the x FETs of the discrete amplitude amplifier of the one stage have coupled in parallel one of gates and drains, and wherein the x/2 FETs of the discrete amplifier of the another stage have coupled in parallel one of gates and drains.

12. The power synthesizer of claim 1 disposed within a mobile station, further comprising an inverse fast fourier transform IFFT block, said IFFT block for converting an amplitude modulated input to a bit modulated output.

30. The power synthesizer of claim 1 wherein each of the n discrete power amplifiers apply a gain that differs from that applied by another nearest-power discrete power amplifier by a fixed amount.

31. The power synthesizer of claim 30 wherein the fixed amount is about 6 dB.

8. (canceled)

13. In a transmitter comprising, in series, an encoder, a serial to parallel converter, a parallel to serial converter for outputting a digital signal at baseband, and at least one transmit antenna, the improvement comprising:

a power synthesizer block comprising at least two discrete amplifier stages in parallel, each stage disposed between the parallel to serial converter and the at least one transmit antenna, and each discrete amplifier stage comprises a discrete amplitude amplifier for applying a gain that differs from that applied by each other discrete amplitude amplifier.

14. In the transmitter of claim 13, the improvement further comprising an absence of a digital to analog converter disposed between the parallel to serial converter and the power synthesizer block.

15. In the transmitter of claim 13, wherein each of the at least two discrete amplifier stages comprises a discrete amplitude amplifier and a modulator in series with one another.

16. In the transmitter of claim 15, the improvement further comprising an inverse fast fourier transform IFFT block disposed between the serial to parallel converter and the parallel to serial converter, the power synthesizer block further comprising a discrete amplitude generator for converting a real valued input from the IFFT block to parallel binary outputs, each parallel binary output coupled to an input of a modulator.

17. In the transmitter of claim 15, the power synthesizer block further comprising at least one power combiner coupling an output of each of the at least two discrete amplifier stages with the at least one transmit antenna.

18. In the transmitter of claim 15, wherein each of the modulators comprises a continuous phase modulator.

19. In the transmitter of claim 15, wherein each of the discrete amplifiers comprises a constant envelope amplifier.

20. In the transmitter of claim 15, the improvement further comprising:

the at least one transmit antenna comprises a first and a second transmit antenna, wherein an output of one of the at least two discrete amplifier stages is coupled to an input of the first transmit antenna and an output of another of the at least two discrete amplifier stages is coupled to an input of the second transmit antenna.

21. In the transmitter of claim 20, the improvement further comprising:

the at least two transmit antennas comprise n transmit antennas and the at least two discrete amplifier stages comprise n discrete amplifier stages, wherein each n^th transmit antenna is coupled to an output of an n^th discrete amplifier stage.

22. In the transmitter of claim 15, the improvement further comprising the transmitter being disposed within a mobile station or a base station.

32. In the transmitter of claim 13, the improvement further comprising each discrete amplitude amplifier for applying a gain that differs by a fixed amount from that applied by its nearest-gain neighbor amplitude amplifier.

33. In the transmitter of claim 32, the improvement further comprising the fixed amount being about 6 dB.

23. A method of transmitting a signal on a multicarrier communication channel comprising:

providing a separate bit of a bit stream on each of n parallel inputs each bit of the bit stream representing a different significance;

for each of the n parallel inputs, controlling a phase of the input bit and amplifying a power of the input bit at a power that is unique respecting all other n parallel inputs;

combining all n phase controlled and amplified bits in one of a spatial manner and a circuit manner.

24. The method of claim 23, wherein combining all amplified and phase controlled bits comprises simultaneously transmitting at least two separately amplified and phase controlled bits by separate transmit antennas.

25. The method of claim 23, wherein controlling a phase of the input bit comprises spectrally shaping the input bit with a continuous phase modulator.

26. The method of claim 25 wherein the modulator comprises a pulse amplitude modulator.

27. The method of claim 25 wherein the modulator approximately performs Gaussian minimum shift keying.

28. The method of claim 25 further comprising, previous to providing a separate bit of a bit stream, converting an amplitude modulated signal to the bit stream.

29. The method of claim 23 wherein combining the amplified phase controlled bits in a circuit manner comprises combining all of the n amplified and phase controlled bits with at least one power combiner prior to transmission.

34. The method of claim 23, wherein amplifying a power of the input bit at a power that is unique respecting all other n parallel inputs comprises, for each of the n parallel inputs, amplifying with a power that differs by a fixed amount from a next nearest power amplification.

35. The method of claim 34, wherein the fixed amount is about 6 dB.

36. A power synthesizer comprising:

a plurality of n stages in parallel with one another, wherein n is an integer at least equal to two, each of the n stages comprising modulating means in series with amplitude amplifying means, wherein each of the n amplitude amplifying means is for applying a gain that is unique as compared to all other of the n amplitude amplifying means; and

actuating means for simultaneously switching the n modulating means.

37. The power amplifier of claim 36, wherein the modulating means comprises a modulator, and the amplitude amplifying means comprise an amplitude amplifier.