Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor

• US 20070099389A1
• Filed: 10/06/2006
• Published: 05/03/2007
• Est. Priority Date: 08/13/2002
• Status: Active Grant

• Current Assignee: Giuseppe Rossi
• Original Assignee: Giuseppe Rossi
• Inventors: Rossi, Giuseppe
• Granted Patent: US 7,681,163 B2
• Time in Patent Office: Days
• US Class Current: 438/393
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

A new capacitor architecture includes a front plate of the capacitor formed from a first polysilicon layer. The front plate is surrounded by a first dielectric layer and a second dielectric layer. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first dielectric layer and the second dielectric layer. The two-layer conductive structure is an equal potential structure and includes a conductive coupling between the two layers.

Claims

1-15. -15. (canceled)

16. An imager, comprising:

a pixel array including pixels for converting light into electrical signals; and

a circuit for sampling signals produced by a pixel, the sampling circuit including

an input line for receiving signals produced by said pixel,

a sample capacitor, and

a switch for controllably coupling said sample capacitor to said input line;

wherein said sample capacitor is fabricated as a semiconductor device and further includes

a front plate comprising a first conductive layer;

a first dielectric layer above and adjacent to said front plate;

a second dielectric layer below and adjacent to said front plate;

a first conductive structure surrounding said first and second dielectric layers,

said conductive structure including a back plate of said capacitor;

a third dielectric layer above and adjacent to said first conductive structure;

a fourth dielectric layer below and adjacent to said first conductive structure; and

a second conductive structure surrounding said third and fourth layers.

17. The imager of claim 16, wherein said first conductive structure further comprises:

a first layer adjacent to a first one of said first and second dielectric layers;

a second layer adjacent to second one of said first and second dielectric layers; and

a conductive interconnect coupling said first and second layers;

wherein,

said first and second layers are conductive;

said first and second layers are equal potential; and

one of said first and second layers forms the back plate of the capacitor.

18. The imager of claim 17, wherein said first one of said first and second dielectric layers is an upper one of said first and second dielectric layers, and said first layer is comprised of a metal layer.

19. The imager of claim 17, wherein said first one of said first and second dielectric layers is an upper one of said first and second dielectric layers, and said first layer is comprised of a polysilicon layer.

20. The imager of claim 17, wherein said second layer comprises polysilicon located below and adjacent to said second dielectric layer.

21. The imager of claim 17, wherein said second layer comprises metal located below and adjacent to said second dielectric layer.

22. The imager of claim 18, wherein said first layer is the back plate of said capacitor.

23. The imager of claim 19, wherein said first layer is the back plate of said capacitor.

24. The imager of claim 16, wherein said second conductive structure further comprises:

a third layer adjacent to a first one of said third and fourth dielectric layers;

a fourth layer adjacent to a second one, different from said first one, of said third and fourth dielectric layers; and

a conductive interconnect coupling said third and fourth layers;

wherein,

said third and fourth layers are conductive; and

said third and fourth layers are equal potential.

25. The imager of claim 24, further comprising:

a second metal layer disposed above an upper one of said third and fourth dielectric layers.

27. The imager of claim 24, wherein said fourth layer is a substrate.

28. The imager of claim 27, wherein said substrate is grounded.

29. The imager of claim 16, wherein said first conductive layer is comprised of polysilicon.

30. The imager of claim 16, wherein said first conductive layer is comprised of a metal.

26. (canceled)

31-54. -54. (canceled)

55. An imager, comprising:

a pixel array including pixels for converting light into electrical signals; and

a circuit for sampling signals produced by a pixel, the sampling circuit including

an input line for receiving signals produced by said pixel,

a sample capacitor, and

a switch for controllably coupling said sample capacitor to said input line;

wherein said sample capacitor is fabricated as a semiconductor device and further includes

a first plate;

a first conductive structure surrounding and thereby shielding said first plate to reduce parasitic capacitance, said first conductive structure further comprising a second plate of said capacitor; and

a second conductive structure surrounding and thereby shielding said first plate and said second plate to reduce parasitic capacitance.

56. The imager of claim 55, wherein said first plate is comprised of polysilicon.

57. The imager of claim 55, wherein said first plate is comprised of a metal.

58. The imager of claim 55, wherein said first conductive structure further comprises,

a second conductive layer;

and

a conductive interconnect conductively coupling said second plate and said second conductive layer.

59. The imager of claim 58, wherein said second conductive layer is comprised of polysilicon.

60. The imager of claim 58, wherein said second conductive layer is comprised of a metal.

61. The imager of claim 55, wherein said second conductive structure further comprises,

a third conductive layer;

a substrate; and

a conductive interconnect coupling said substrate and said third conductive layer.

62. The imager of claim 61, wherein said third conductive layer comprises polysilicon.

63. The imager of claim 61, wherein said third conductive layer comprises a metal.

64-72. -72. (canceled)

73. An imager, comprising:

a pixel array including pixels for converting light into electrical signals;

a circuit for sampling signals produced by a pixel, the sampling circuit including

an input line for receiving signals produced by said pixel,

a sample capacitor, and

a switch for controllably coupling said sample capacitor to said input line;

wherein said sample capacitor is fabricated as a semiconductor device and further includes

a first plate,

a second plate,

a first shield, said first shield including a first surface and a second surface, said first surface and said second surface being equal potential surfaces, and

a second shield, said second shield including a third surface and a fourth surface, said third surface and said fourth surface being equal potential surfaces;

wherein

said first plate and said second plate are disposed to form two plates of said capacitor,

said first surface and said second surface are disposed to shield said first plate to reduce parasitic capacitance,

and said third surface and said fourth surface are disposed to shield said first plate and said second plate to reduce parasitic capacitance.

74. The imaging system of claim 73, wherein said second shield is disposed to also shield said first shield.

75. The imaging systems of claim 73, wherein said capacitor is formed over a substrate.

76. The imaging system of claim 75, wherein one of said first surface and said second surface is a polysilicon layer formed over said substrate.

77. The imaging system of claim 75, wherein one of said first surface and said second surface is a metal layer formed over said substrate.

78. The imaging system of claim 75, wherein one of said third surface and said fourth surface is said substrate formed over said substrate.

79. The imaging system of claim 75, wherein one of said third surface and said fourth surface is a metal layer formed over said substrate.

80. The imaging system of claim 75, wherein one of said first plate and said second plate is a metal layer formed over said substrate.

81. The imaging system of claim 75, wherein one of said first plate and said second plate is a polysilicon layer formed over said substrate.