METHOD AND APPARATUS FOR PROVIDING CONTEXT SWITCHING OF LOGIC IN AN INTEGRATED CIRCUIT

• US 20070101108A1
• Filed: 11/03/2005
• Published: 05/03/2007
• Est. Priority Date: 11/03/2005
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Grossman, Mark, Buchner, Gregory
• Granted Patent: US 7,461,242 B2
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context

Abstract

A method and apparatus provides context switching of logic in an integrated circuit using one or more test scan circuits that use test data during a test mode of operation of the integrated circuit to store and/or restore non-test data during normal operation of the integrated circuit. The integrated circuit includes context control logic operative to control the test scan circuit to at least one of: store and restore context state information contained in functional storage elements in response to detection of a request for a change in context during normal operation of the integrated circuit.

Claims

1. A method for providing context switching in an integrated circuit comprising:

detecting a request for a change in context for at least one of a plurality of logic circuits in the integrated circuit; and

controlling at least one test scan circuit associated with the at least one of the logic circuits to at least one of;

save and restore context state information of the at least one of the logic circuits in response to the request for a change in context.

2. The method of claim 1 wherein the plurality of logic circuits comprises at least one memory client.

3. The method of claim 2 wherein controlling the test scan circuit comprises selecting at least one flop scan chain of the test scan circuit to at least one of:

output context state information for transfer to memory for storage and receive stored context state information from memory.

4. The method of claim 2 including at least one of:

compressing the context state information prior to storing the context state information in the memory and decompressing compressed context state information prior to restoring the context state information using the test scan circuit.

5. The method of claim 1 wherein controlling the test scan circuit comprises controlling switching logic that is operatively coupled to the logic circuits to store and restore context state information of the logic circuits.

6. The method of claim 1 wherein saving a first set of context state information is performed simultaneously with restoring a second set of context state information.

7. The method of claim 1 wherein context state information comprises data stored in flip flops and in RAM elements.

8. The method of claim 1 including stalling the save and/or restore of the context state information in response to a memory controller loading level.

9. The method of claim 1 wherein the test scan circuit comprises memory wrapper logic and wherein the memory wrapper logic is used to save and restore one or more serial streams of state information.

10. The method of claim 1 including performing error detection and correction on the context state information to be stored in memory.

11. A method for providing context switching of memory clients in an integrated circuit comprising:

providing real time state management and providing virtual address maintenance for a particular memory client by controlling a built in test scan circuit to store context state information during a non-test mode operation of the integrated circuit; and

storing the context state information.

12. The method of claim 11 including at least one of:

compressing the context state information prior to storing the context state information in the memory and decompressing compressed context state information prior to restoring the context state information using the built in test scan circuit.

22. The circuit of claim 12 wherein the at least one test scan circuit is operative to use test data during a test mode and operatively coupled to use data during normal operation comprises a context state information restore circuit comprising:

a deserializing circuit;

parallel test scan chains each having an input operatively coupled to receive data from the deserializing circuit; and

a serializing circuit, operatively coupled to an output of each of the parallel test scan chains.

13. An integrated circuit comprising:

at least one test scan circuit operative to use test data during a test mode and operatively coupled to use non-test data during normal operation; and

context control logic operative to control the test scan circuit to at least one of;

store and restore context state information of the test scan circuit in response to detection of a request for a change in context during normal operation.

14. The circuit of claim 13 wherein the test scan circuit comprises a plurality of scan chains of at least one of:

latch elements and at least one random access memory array and wherein the context control logic is operative to select inputs to each of the plurality of scan chains to facilitate restoring of the context state information from memory during non-test operation.

15. The circuit of claim 13 wherein the test scan circuit comprises at least one scan chain comprising a switching structure operatively coupled to an input latch element of the scan chain and operatively controllable to select as input to the input latch element at least one of:

input data from a logic circuit, test data and restore context state information.

16. The circuit of claim 15 wherein the scan chain comprises an output latch element having an output operatively coupled to the context control logic to provide context state information for storage in response to a context state change.

17. The circuit of claim 13 including clock switching logic and wherein the context control logic is operative to control clocking of the logic circuit during non-test operation to at least one of save and restore context state information.

18. The circuit of claim 13 comprising memory control logic operatively coupled to the context control logic and operative to provide parallel store and retrieve operations for a memory client and save and restore of context state information via the context control logic.

19. The circuit of claim 13 wherein the plurality of logic circuits comprise logic circuits in a graphics engine.

20. The circuit of claim 13 comprising memory control logic operatively coupled to the context control logic and coupleable to memory and operative to facilitate storage and retrieval of the context state information to and from the memory.

21. The circuit of claim 13 wherein the plurality of logic circuits comprise at least one memory client.

23. An integrated circuit comprising:

at least one test scan circuit comprising parallel scan chains of at least latch elements and at least one random access memory array; and

context control logic operative to control the test scan circuit to at least one of;

save and restore context state information of the logic circuits in response to the detection of a request for a change in context during non-test operation of the logic circuits.

26. The integrated circuit of claim 23 comprising a plurality of serially coupled RAM elements each having associated test scan circuits and wherein the context control logic is operative to shift context information from one RAM element to the other RAM element during normal operation and multiplexing saved context in a data path to a memory controller.

27. The integrated circuit of claim 23 comprising a plurality of RAM elements each having associated test scan circuits and wherein the context control logic is operative to shift context information from one RAM element during one set of clock cycles and from another RAM element during another set of clock cycles.

24. An integrated circuit comprising:

at least one random access memory array;

at least one test scan circuit operatively coupled to the RAM array and operative to test the RAM array during a test mode; and

context control logic operative to control the test scan circuit to at least one of;

store and restore context information from and to the RAM array, in response to the detection of a change in context during non-test operation of the RAM array.

25. The integrated circuit of claim 24 comprising at least one logic circuit operatively coupled to the RAM array and operative to use the RAM array to store data during normal operation of the logic circuit.

28. A method of providing context switching on an IC comprising:

executing a first context on the IC;

suspending execution of said first context;

storing a first set of context state information from said first context to memory using a test circuit;

executing a second context on the IC;

suspending execution of said second context;

loading said first set of context state information from memory using said test circuit; and

continuing execution of the first context.

29. The method of claim 28 wherein the context switching is executed while the IC is in an operational mode.

30. The method of claim 29 comprising the additional steps of placing the IC in a test mode and using the test circuit for testing purposes.

31. A method of providing context switching on an IC comprising:

at least one of;

serially shifting in new context state information and shifting out current context state information using a test circuit;

at least one of;

simultaneously reading the new context state information and writing current context state information to memory; and

inhibiting the serial shifting based on the availability of both memory read and write capability.

32. A method for providing context switching in an integrated circuit comprising:

controlling at least one built in self test scan circuit to at least one of store context state information and restore context state information during a non-self test mode of operation of the integrated circuit; and

at least one of;

storing context state information in memory and retrieving stored context information from memory to restore context state information for the integrated circuit in response to the controlling of the at least one built in self test circuit.

33. An integrated circuit comprising:

at least one built in self test scan circuit operative during a test mode of the integrated circuit; and

context control logic operative to control the built in self test scan circuit of the integrated circuit during a non test mode to at least one of;

store and restore context state information of the test scan circuit in response to detection of a request for a change in context during normal operation.