APPARATUS AND METHOD FOR MEMORY READ-REFRESH, SCRUBBING AND VARIABLE-RATE REFRESH
First Claim
1. An information-processing apparatus comprising:
- a first memory controller comprising;
a memory-chip interface that outputs memory addresses in a plurality of portions, including a first-address portion that is sufficient to refresh a set of addresses for a portion of a memory and a second-address portion that specifies one or more locations within the set of addresses; and
a refresh controller, coupled to the memory-chip interface, and configured to send read-refresh requests, wherein the read-refresh requests use refresh addresses that cycle through address-bit combinations for the first-address portion and also cycle through address-bit combinations for the second-address portion, and wherein read-refresh result data is fetched to the memory-chip interface as a result of each of the read-refresh requests.
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Accused Products
Abstract
A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
104 Citations
46 Claims
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1. An information-processing apparatus comprising:
a first memory controller comprising;
a memory-chip interface that outputs memory addresses in a plurality of portions, including a first-address portion that is sufficient to refresh a set of addresses for a portion of a memory and a second-address portion that specifies one or more locations within the set of addresses; and
a refresh controller, coupled to the memory-chip interface, and configured to send read-refresh requests, wherein the read-refresh requests use refresh addresses that cycle through address-bit combinations for the first-address portion and also cycle through address-bit combinations for the second-address portion, and wherein read-refresh result data is fetched to the memory-chip interface as a result of each of the read-refresh requests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An information-processing method comprising:
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sending a stream of processor memory requests to memory parts;
inserting a read-refresh request periodically into the stream of processor memory requests, wherein the periodic read-refresh requests are sent using refresh addresses that cycle through a first set of address bits sufficient for refreshing the memory parts and also cycle through a second set of address bits sufficient to read substantially all data locations in the memory parts; and
fetching data as a result of each of the read-refresh requests. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. An information-processing system comprising:
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a plurality of memory chips;
a memory-request buffer, coupled to the memory chips, and configured to hold one or more pending memory requests from a processor that are transmitted to the memory chips; and
means for read-refreshing the memory chips and fetching read-refresh data as a result. - View Dependent Claims (36, 37, 38, 39, 40)
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41. An information-processing system comprising:
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a dynamic memory, wherein the dynamic memory includes a first plurality of memory locations, and wherein a sufficient subset of the first plurality of memory locations must each be accessed within a refresh-period amount of time;
a memory controller, coupled to the memory, and configurable to perform a first read operation to each and every one of the first plurality of memory locations, each first read operation causing corresponding read-refresh data to be fetched in a pattern that ensures that the sufficient subset is read within the refresh-period amount of time; and
an error detector operatively coupled to receive and check for errors the corresponding read-refresh data. - View Dependent Claims (42, 43, 44, 45, 46)
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Specification