Reconfigurable communications infrastructure for ASIC networks

• US 20070101242A1
• Filed: 11/16/2006
• Published: 05/03/2007
• Est. Priority Date: 05/11/2004
• Status: Active Grant

• Current Assignee: Lionra Technologies Limited (Atlantic IP Services Limited)
• Original Assignee: L-3 Communications Integrated Systems LP (L3Harris Technologies, Inc.)
• Inventors: Yancey, Jerry, Kuo, Yea
• Granted Patent: US 7,921,323 B2
• Time in Patent Office: Days
• US Class Current: 714/776
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

Reconfigurable communications infrastructures may be implemented to interconnect ASIC devices (e.g., FPGAs) and other computing and input/output devices using high bandwidth interconnection mediums. The computing and input/output devices may be positioned in locations that are physically segregated from each other, and/or may be provided to project a reconfigurable network across a wide area. The reconfigurable communications infrastructures may be implemented to allow such computing and input/output devices to be used in different arrangements and applications, e.g., for use in any application where a large array of ASIC devices may be usefully employed such as supercomputing, etc.

Claims

1. A method, comprising:

providing two or more ASIC devices, each one of said two or more ASIC devices comprising a packet router;

providing a high bandwidth interconnection medium coupled between said packet routers of each of said two or more ASIC devices to form a reconfigurable communications infrastructure; and

communicating data between said packet routers of each of said two or more ASIC devices across said high bandwidth interconnection medium.

2. The method of claim 1, wherein each of said two or more ASIC devices comprises FPGA devices.

3. The method of claim 2, further comprising:

providing said two or more FPGA devices by providing two or more signal processing circuits, each one of said two or more signal processing circuits comprising at least one FPGA device that comprises a packet router;

providing said high bandwidth interconnection medium coupled between said two or more signal processing circuits to provide data communication between said packet routers of said FPGA devices of each of said two or more signal processing circuits; and

communicating data across said high bandwidth interconnection medium between said packet routers of said FPGA devices of each of said two or more signal processing circuits.

4. The method of claim 3, wherein at least one of said signal processing circuits is a reconfigurable signal processing circuit that further comprises two or more FPGA devices that each comprise a packet router, said packet router of each one of said two or more FPGA devices of said at least one signal processing circuit being coupled to each respective packet router of each of the other of said two or more FPGA devices of said at least one signal processing circuit;

and wherein said method further comprises using said packet router of each given one of said two or more FPGA devices of said at least one signal processing circuit to communicate data packets with each other of said two or more FPGA devices of said at least one signal processing circuit.

5. The method of claim 4, wherein said packet router of each one of said two or more FPGA devices of said at least one signal processing circuit is coupled to each respective packet router of each of the other of said two or more FPGA devices of said at least one signal processing circuit by a separate respective duplex data communication link so as to form a direct serial interconnection between each two of said two or more FPGA devices of said signal processing circuit;

and wherein said method further comprises using said packet router of each given one of said two or more FPGA devices of said at least one signal processing circuit to transmit and receive data packets across each of said separate respective duplex data communication links existing between said given one of said two or more FPGA devices and each other of said two or more FPGA devices of said at least one signal processing circuit.

6. The method of claim 2, wherein each given one of said two or more FPGA devices comprises user-defined circuitry coupled to said respective packet router of said given one of said two or more FPGA devices;

and wherein said method further comprises transmitting and receiving data packets between said user-defined circuitry of said given one of said two or more FPGA devices and said high bandwidth interconnection medium.

7. The method of claim 2, wherein each given one of said two or more FPGA devices comprises at least one embedded processor coupled to said respective packet router of said given one of said two or more FPGA devices;

and wherein said method further comprises transmitting and receiving data packets between said at least one embedded processor of said given one of said two or more FPGA devices and said high bandwidth interconnection medium.

8. The method of claim 2, further comprising providing a vehicle-based reconfigurable communications infrastructure comprising a vehicle with each of said two or more FPGA devices and said high bandwidth interconnection medium being positioned on or within said vehicle;

and communicating data between said packet routers of each of said two or more FPGA devices across said high bandwidth interconnection medium on or within said vehicle.

9. The method of claim 2, further comprising providing said two or more FPGA devices in positions physically segregated from each other;

and communicating data between said packet routers of each of said two or more physically-segregated FPGA devices across said high bandwidth interconnection medium.

10. The method of claim 2, wherein said high bandwidth interconnection medium comprises an optical transmission medium;

and wherein said method further comprises communicating data between said packet routers of each of said two or more FPGA devices across said optical transmission medium.

11. The method of claim 2, further comprising communicating data between said packet routers of each of said two or more FPGA devices at a data transmission rate of greater than or equal to about 1 Gbps.

12. The method of claim 2, further comprising configuring each of said at least two FPGA devices to perform different computing tasks in parallel.

13. The method of claim 2, further comprising:

providing said two or more FPGA devices as first and second FPGA devices;

configuring said first and second FPGA devices to perform a first computing task together as a first computing cluster;

providing at least two additional FPGA devices as third and fourth FPGA devices, each one of said third and fourth FPGA devices comprising a packet router coupled to said high bandwidth interconnection medium;

configuring said third and fourth FPGA devices to perform a second computing task together as a second computing cluster, said second computing task being different than said first computing task; and

simultaneously performing said first computing task with said first computing cluster and said second computing task with said second computing cluster.

14. The method of claim 13, further comprising:

reconfiguring said first and third FPGA devices to perform a third computing task together as a third computing cluster;

configuring said second and fourth FPGA devices to perform a fourth computing task together as a fourth computing cluster, said fourth computing task being different than said third computing task; and

simultaneously performing said third computing task with said third computing cluster and said fourth computing task with said fourth computing cluster.

15. The method of claim 13, further comprising:

reconfiguring said first, second, third and fourth FPGA devices to perform a third computing task together as a third computing cluster; and

performing said third computing task with said third computing.

16. A reconfigurable communications infrastructure, comprising:

two or more ASIC devices, each one of said two or more ASIC devices comprising a packet router; and

a high bandwidth interconnection medium coupled between said packet routers of each of said two or more ASIC devices to provide data communication between said packet routers of each of said two or more ASIC devices.

17. The reconfigurable communications infrastructure of claim 16, wherein each of said two or more ASIC devices comprises FPGA devices.

18. The reconfigurable communications infrastructure of claim 17, further comprising:

two or more signal processing circuits, each one of said two or more signal processing circuits comprising at least one FPGA device that comprises a packet router; and

wherein said high bandwidth interconnection medium is coupled between said two or more signal processing circuits to provide data communication between said packet routers of said FPGA devices of each of said two or more signal processing circuits.

19. The reconfigurable communications infrastructure of claim 18, wherein at least one of said signal processing circuits is a reconfigurable signal processing circuit that further comprises two or more FPGA devices that each comprise a packet router, said packet router of each one of said two or more FPGA devices of said at least one signal processing circuit being coupled to each respective packet router of each of the other of said two or more FPGA devices of said at least one signal processing circuit.

20. The reconfigurable communications infrastructure of claim 19, wherein said packet router of each one of said two or more FPGA devices of said at least one signal processing circuit is coupled to each respective packet router of each of the other of said two or more FPGA devices of said at least one signal processing circuit by a separate respective duplex data communication link so as to form a direct serial interconnection between each two of said two or more FPGA devices of said signal processing circuit.

21. The reconfigurable communications infrastructure of claim 17, wherein each given one of said two or more FPGA devices comprises user-defined circuitry coupled to said respective packet router of said given one of said two or more FPGA devices;

and wherein said respective packet router of each given one of said two or more FPGA devices is configured to transmit and receive data packets between said user-defined circuitry of said given one of said two or more FPGA devices and said high bandwidth interconnection medium.

22. The reconfigurable communications infrastructure of claim 17, wherein each given one of said two or more FPGA devices comprises at least one embedded processor coupled to said respective packet router of said given one of said two or more FPGA devices;

and wherein said respective packet router of each given one of said two or more FPGA devices is configured to transmit and receive data packets between said at least one embedded processor of said given one of said two or more FPGA devices and said high bandwidth interconnection medium.

23. The reconfigurable communications infrastructure of claim 17, wherein said reconfigurable communications infrastructure is a vehicle-based reconfigurable communications infrastructure comprising a vehicle;

and wherein each of said two or more FPGA devices is positioned on or within said vehicle.

24. The reconfigurable communications infrastructure of claim 17, wherein said two or more FPGA devices are physically segregated from each other.

25. The reconfigurable communications infrastructure of claim 17, wherein said high bandwidth interconnection medium comprises an optical transmission medium.

26. The reconfigurable communications infrastructure of claim 17, wherein said high bandwidth interconnection medium comprises an interconnection medium having a data transmission capability of greater than or equal to about 1 Gbps.

27. A communications infrastructure, comprising two or more ASIC devices, each one of said two or more ASIC devices comprising a packet router, said packet router of each one of said two or more ASIC devices being coupled to each respective packet router of each of the other of said two or more ASIC devices by an interconnection comprising a high speed serial optical link.

28. The communications infrastructure of claim 27, wherein said interconnection further comprises a high bandwidth interconnection medium.

29. The communications infrastructure of claim 28, wherein each of said two or more ASIC devices comprises FPGA devices.

30. The communications infrastructure of claim 29, further comprising:

two or more signal processing circuits, each one of said two or more signal processing circuits comprising at least one FPGA device that comprises a packet router; and

wherein said interconnection is coupled between said two or more signal processing circuits to provide data communication between said packet routers of said FPGA devices of each of said two or more signal processing circuits.

31. A method, comprising:

providing two or more ASIC devices, each one of said two or more ASIC devices comprising a packet router coupled together by an interconnection comprising a high speed serial optical link, and

transferring at least one data packet from each said packet router of each one of said two or more ASIC devices to each respective packet router of each of the other of said two or more ASIC devices by said high speed serial optical link.

32. The method of claim 31, wherein said interconnection further comprises a high bandwidth interconnection medium.

33. The method of claim 32, wherein each of said two or more ASIC devices comprises FPGA devices.

34. The method of claim 33, further comprising:

providing said two or more FPGA devices by providing two or more signal processing circuits, each one of said two or more signal processing circuits comprising at least one FPGA device that comprises a packet router;

providing said interconnection coupled between said two or more signal processing circuits to provide data communication between said packet routers of said FPGA devices of each of said two or more signal processing circuits; and

communicating data across said interconnection between said packet routers of said FPGA devices of each of said two or more signal processing circuits.