FinFET transistor fabricated in bulk semiconducting material

• US 20070102756A1
• Filed: 11/10/2005
• Published: 05/10/2007
• Est. Priority Date: 11/10/2005
• Status: Abandoned Application

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lojek, Bohumil
• Application Number:
  US11/271,375
• Publication Number:
  US 20070102756A1
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from bulk semiconductor wafers, as opposed to silicon-on-insulator (SOI) or separation by implantation of oxygen (SIMOX) wafers, in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices from readily-available bulk semiconductor substrates with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.

Claims

1. A method for forming an electronic device, the method comprising:

providing a substrate;

forming a fin on the substrate, the fin being produced in a bulk semiconducting material of the substrate, the fin having a given width;

filling a space on either side of the fin with a non-conducting material;

etching back an uppermost portion of the non-conducting material such that a given height of the fin is exposed above the etched-back portion of the non-conducting material;

forming a thin oxide over the fin; and

forming a semiconducting gate region over the thin oxide, the semiconducting gate region covering a channel, the channel being doped with a first type of majority carrier.

2. The method of claim 1, further comprising doping portions of the fin not covered by the semiconducting gate region, the dopant having a second type of majority carrier.

3. The method of claim 1 wherein the fin is formed from a substrate being comprised of bulk silicon.

4. The method of claim 3 wherein an orientation of the bulk silicon is chosen so as to enhance electrical performance of the device.

5. The method of claim 1 wherein the fin is formed from a substrate comprised of a strain-compensated semiconducting material.

6. The method of claim 1 wherein the width of the fin is formed to be less than 100 nm.

7. The method of claim 1 wherein the height of the fin is formed to be in a range of approximately 100 nm to 500 nm.

8. The method of claim 1, further comprising:

forming a first dielectric layer on the substrate prior to forming the fin, the first dielectric layer being comprised of a first type of dielectric material;

forming a second dielectric layer over the substrate prior to forming the fin, the second dielectric layer being comprised of a second type of dielectric material; and

forming a dielectric material on sidewalls of the fin after the fin has been formed.

9. The method of claim 8 wherein a planarization step of the non-conducting material occurs prior to etching back an uppermost portion of the non-conducting material and is accomplished by chemically mechanically planarizing the material.

10. An electronic device, comprising:

a fin fabricated from a bulk semiconducting material;

a gate region comprised of a semiconducting material, the gate region overlying a first portion of the fin, the first portion of the fin being doped with a majority carrier of a first type; and

a drain region formed on a second portion of the fin, the drain region being located on a first side of the gate region, the drain region being doped with a majority carrier of a second type.

11. The electronic device of claim 10 further comprising a source region formed on a third portion of the fin, the source region being distal to the drain region and located on a second side of the gate region, the source region being doped with the majority carrier of the second type.

12. The device of claim 10 wherein the bulk semiconducting material is silicon.

13. The method of claim 12 wherein a sidewall of the fin is fabricated in any appropriate crystallographic plane of the bulk silicon.

14. An electronic device, comprising:

a fin on a substrate, the substrate comprising a bulk semiconducting material, the fin being fabricated by steps including;

(i) producing the fin in the bulk semiconducting material of the substrate, the fin having a given width;

(ii) filling a space on either side of the fin with a non-conducting material;

(iii) etching back an uppermost portion of the non-conducting material such that a given height of the fin is exposed above the etched-back portion of the non-conducting material; and

(iv) forming a thin oxide over the fin;

a gate region comprised of a semiconducting material, the gate region overlying a first portion of the fin, the first portion of the fin being doped with a majority carrier of a first type;

a drain region formed on a second portion of the fin, the drain region being located on a first side of the gate region, the drain region being doped with a majority carrier of a second type; and

a source region formed on a third portion of the fin, the source region being distal to the drain region and located on a second side of the gate region, the source region being doped with the majority carrier of the second type.

15. The device of claim 14 wherein the bulk semiconducting material is silicon.

16. The device of claim 15 wherein a sidewall of the fin is fabricated in any appropriate crystallographic plane of the bulk silicon.

17. The device of claim 14 wherein the bulk semiconducting material is comprised of a strain-compensated compound semiconductor.

18. A method for forming an electronic device, the method comprising:

providing a bulk silicon substrate;

forming a fin from the silicon substrate, the fin having a given width;

forming a first dielectric layer on the silicon substrate prior to forming the fin, the first dielectric layer being comprised of a first type of dielectric material;

forming a second dielectric layer over the substrate prior to forming the fin, the second dielectric layer being comprised of a second type of dielectric material;

forming a dielectric material on sidewalls of the fin after the fin has been formed;

filling a space on either side of the fin with a non-conducting material;

etching back an uppermost portion of the non-conducting material such that a given height of the fin is exposed above the etched-back portion of the non-conducting material;

forming a thin oxide over the fin;

forming a semiconducting gate region over the thin oxide, the semiconducting gate region covering a channel, the channel being doped with a first type of majority carrier; and

doping portions of the fin not covered by the semiconducting gate region, the dopant having a second type of majority carrier.

19. The method of claim 18 wherein the first dielectric layer is comprised of silicon dioxide.

20. The method of claim 18 wherein the second dielectric layer is comprised of silicon nitride.

21. The method of claim 18 wherein a sidewall of the fin is fabricated in any appropriate crystallographic plane of the bulk silicon.

22. The method of claim 18 wherein an orientation of the bulk silicon is chosen so as to enhance electrical performance of the device.

23. The method of claim 18 wherein the width of the fin is formed to be less than 100 nm.

24. The method of claim 18 wherein the height of the fin is formed to be in a range of approximately 100 nm to 500 nm.

25. A method for forming an electronic device, the method comprising:

providing a substrate;

forming a fin on the substrate, the fin being produced in a bulk semiconducting material of the substrate, the fin having a given width;

filling a space on either side of the fin with a non-conducting material until a given height of the fin is exposed above the substrate;

forming a thin oxide over the fin;

forming a semiconducting gate region over the thin oxide, the semiconducting gate region covering a channel, the channel being doped with a first type of majority carrier; and

doping portions of the fin not covered by the semiconducting gate region, the dopant having a second type of majority carrier.

26. The method of claim 25 wherein the width of the fin is formed to be less than 100 nm.

27. The method of claim 25 wherein the height of the fin is formed to be in a range of approximately 100 nm to 500 nm.

28. The method of claim 25, further comprising:

forming a first dielectric layer on the substrate prior to forming the fin, the first dielectric layer being comprised of a first type of dielectric material;

forming a second dielectric layer over the substrate prior to forming the fin, the second dielectric layer being comprised of a second type of dielectric material; and

forming a dielectric material on sidewalls of the fin after the fin has been formed.

29. An electronic device, comprising:

a fin on a substrate, the substrate comprising a bulk semiconducting material, the fin being fabricated by steps including;

(i) producing the fin in the bulk semiconducting material of the substrate, the fin having a given width;

(ii) filling a space on either side of the fin with a non-conducting material until a given height of the fin is exposed above the substrate; and

(iii) forming a thin oxide over the fin;

a gate region comprised of a semiconducting material, the gate region overlying a first portion of the fin, the first portion of the fin being doped with a majority carrier of a first type; and

a drain region formed on a second portion of the fin, the drain region being located on a first side of the gate region, the drain region being doped with a majority carrier of a second type.

30. The device of claim 29, further comprising a source region formed on a third portion of the fin, the source region being distal to the drain region and located on a second side of the gate region, the source region being doped with the majority carrier of the second type.

31. The device of claim 29 wherein the bulk semiconducting material is silicon.

32. The device of claim 31 wherein a sidewall of the fin is fabricated in any appropriate crystallographic plane of the bulk silicon.