POWER DISTRIBUTION FOR HIGH-SPEED INTEGRATED CIRCUITS

• US 20070102806A1
• Filed: 12/01/2006
• Published: 05/10/2007
• Est. Priority Date: 11/08/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Horn, Kevin, Dillinger, Forest, Sauter, Karl, Buhler, Otto
• Granted Patent: US 7,919,804 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/024 Dielectric details, e.g. changing the dielectric material around a transmission line
• CPC Class Codes: H05K 2201/0187 with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array

Abstract

An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.

Claims

1. A carrier for at least one electronic device, comprising:

a substrate;

a first conductive layer disposed above the substrate;

a dielectric layer disposed above the first conductive layer, wherein the dielectric layer comprises a first region having a high Er material and a second region having a low Er material; and

a second conductive layer disposed above the dielectric layer.

2. The carrier of claim 1 wherein the first region is disposed above and around the second region such that at a portion of the first region is above the second region and a portion of the first region is coplanar and laterally adjacent to the second region.

3. The carrier of claim 1 further comprising a third conductive layer disposed between the first and second conductive layers and between at least a portion of the first and second regions.

4. The carrier of claim 3 further comprising a via fence for electrical interconnect of the second and third conducting layers such that the second and third conductive layers have the same electric potential.

5. The carrier of claim 3 in combination with an integrated circuit device having an outer peripheral that defines an IC footprint on a top surface of the carrier, and wherein the at least one second region is at least partially underneath the IC footprint.

6. The combination of claim 5 further comprising a plurality of decoupling capacitors adjacent to the integrated circuit device, and wherein the second region extends laterally outward beyond the IC footprint to also be underneath the plurality of decoupling capacitors.

7. The combination of claim 6 wherein the third conductive layer substantially corresponds with the lateral extension of the second region.

8. The combination of claim 6 further comprising an additional integrated circuit defining an additional IC footprint and additional decoupling capacitors adjacent to the additional integrated circuit device, and wherein the dielectric layer further includes a third region having a low Er material that extends laterally outward beyond the additional IC footprint to also be underneath the plurality of additional decoupling capacitors, wherein the second and third regions are discontinuous.

9. The combination of claim 8 wherein the first region is disposed above and around the second and third regions such that a portion of the first region is above the second and third regions and a portion of the first region is coplanar to and laterally adjacent to both of the second and third regions.

10. The combination of claim 9 wherein the portion of the first region that is coplanar to and laterally adjacent to both of the second and third regions is between the second and third regions.

11. An electronic assembly, comprising:

a circuit board;

an integrated circuit attached to the printed circuit board; and

a decoupling capacitor attached to the circuit board, and proximate to the at least one integrated circuit device, wherein the circuit board comprises an inner dielectric layer comprising (i) a first material having a relatively high dielectric constant, and (ii) a second material having a relatively low dielectric constant.

12. The electronic assembly of claim 11 wherein the first region is disposed above and around the second region such that at a portion of the first region is above the second region and a portion of the first region is coplanar and laterally adjacent to the second region.

13. The carrier of claim 12 further comprising a third conductive layer disposed between the first and second conductive layers and between at least a portion of the first and second regions.

14. The carrier of claim 13 further comprising a via fence for electrical interconnect of the second and third conducting layers such that the second and third conductive layers have the same electric potential.

15. The carrier of claim 14 wherein the second material and third conducting layer are disposed below a power pin of the integrated circuit and below the decoupling capacitor

16. A buried capacitance structure within a carrier device for electronic components, comprising:

a first ground layer comprising an electrically conductive material;

a second ground layer comprising the electrically conductive material;

a power layer comprising the electrically conductive material; and

a dielectric layer having at least two separate regions, with one region consisting of high dielectric material and another region consisting of low dielectric material, wherein the low dielectric region is disposed between the first ground layer and the power layer and the high dielectric region is disposed above the first ground layer, below the second ground layer, and around the low dielectric region.

17. The buried capacitance structure of claim 16 wherein the first ground layer is electrically interconnected to the second ground layer.

18. The buried capacitance structure of claim 16 wherein the high dielectric material is one of barium titanate, tantalum oxide, aluminum oxide, alumina, borosilicate and mica.

19. The buried capacitance structure of claim 16 wherein the low dielectric material is a polymer film.

20. The buried capacitance structure of claim 16 wherein a dielectric differential between the high dielectric material and the low dielectric material is at least 1.