Universal wafer carrier for wafer level die burn-in

• US 20070103180A1
• Filed: 10/27/2006
• Published: 05/10/2007
• Est. Priority Date: 08/29/1990
• Status: Abandoned Application

• Current Assignee: Alan Wood, Tim Corbett
• Original Assignee: Alan Wood, Tim Corbett
• Inventors: Wood, Alan, Corbett, Tim
• Application Number:
  US11/588,707
• Publication Number:
  US 20070103180A1
• Time in Patent Office: Days
• US Class Current: 324/750.250
• CPC Class Codes: G01R 1/0466 concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2867 Handlers or transport devices, e.g. loaders, carriers, trays
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/2893 Handling, conveying or loading, e.g. belts, boats, vacuum fingers G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H01L21/67
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H05K 2201/0133 : Elastomeric or compliant polymer elastomeric conductor H05K2201/0314
• CPC Class Codes: H05K 2201/0347 : Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias reinforcing the conductive pattern H05K3/24
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/0394 : Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2201/09481 : Via in pad; Pad over filled via if used for surface mounting H05K1/113
• CPC Class Codes: H05K 2201/09563 : Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2203/0307 : Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
• CPC Class Codes: H05K 2203/0723 : Electroplating, e.g. finish plating
• CPC Class Codes: H05K 3/0058 : Laminating printed circuit boards onto other substrates, e.g. metallic substrates H05K1/0281 takes precedence
• CPC Class Codes: H05K 3/0067 : onto an inorganic, non-metallic substrate
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/423 : characterised by electroplating method

Abstract

A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Claims

1. A wafer testing apparatus comprising:

a first rigid support member and a second rigid support member for receiving a plurality of semiconductor dice on a wafer therebetween, one of the first rigid support member and the second rigid support member including a single cavity for retaining the plurality of semiconductor dice on a wafer therein during testing;

a plurality of contact members formed on the first rigid support member for communicating with electrical connectors for connecting to external test circuitry;

a single biasing assembly including a single floating platform having a preselected area substantially sized to correspond with the single cavity and an elastomeric member disposed on the second rigid support member, the single biasing assembly sized for uniformly biasing the plurality of semiconductor dice on a wafer towards the plurality of contact members, the single floating platform directly supporting the wafer with the elastomeric member sandwiched between the single floating platform and the second rigid support member.

2. The apparatus as claimed in claim 1, further comprising an alignment device for aligning the first rigid support member and the second rigid support member with one another.

3. The apparatus as claimed in claim 1, further comprising an alignment device including a dowel on one of the first rigid support member and the second rigid support member and a corresponding opening on the other of the first rigid support member and the second rigid support member.

4. A testing apparatus for use with wafers comprising:

a first rigid support member and a second rigid support member for receiving a plurality of semiconductor dice on a wafer therebetween, one of the first rigid support member and the second rigid support member including a single cavity for retaining the plurality of semiconductor dice on a wafer therein during testing;

a plurality of contact members formed on the first rigid support member for communicating with electrical connectors for connecting to external test circuitry;

a single biasing assembly including a single floating platform having a preselected area substantially sized to correspond with the single cavity and an elastomeric member disposed on the second rigid support member, the single biasing assembly sized for uniformly biasing the plurality of semiconductor dice on a wafer towards the plurality of contact members, the single floating platform directly supporting the wafer with the elastomeric member sandwiched between the single floating platform and the second rigid support member.

5. The apparatus as claimed in claim 4, further comprising an alignment device for aligning the first rigid support member and the second rigid support member with one another.

6. The apparatus as claimed in claim 4, further comprising an alignment device including a dowel on one of the first rigid support member and second rigid support member and a corresponding opening on the other of the first rigid support member and the second rigid support member.

7. A testing apparatus comprising:

a first rigid support member and a second rigid support member for receiving a plurality of semiconductor dice on a wafer therebetween, one of the first rigid support member and the second rigid support member including a single cavity for retaining the plurality of semiconductor dice on a wafer therein during testing;

a plurality of contact members formed on the first rigid support member for communicating with electrical connectors for connecting to external test circuitry;

a single biasing assembly including a single floating platform having a preselected area substantially sized to correspond with the single cavity and an elastomeric member disposed on the second rigid support member, the single biasing assembly sized for uniformly biasing the plurality of semiconductor dice on a wafer towards the plurality of contact members, the single floating platform directly supporting the wafer with the elastomeric member sandwiched between the single floating platform and the second rigid support member.

8. The apparatus as claimed in claim 7, further comprising an alignment device for aligning the first rigid support member and the second rigid support member with one another.

9. The apparatus as claimed in claim 7, further comprising an alignment device including a dowel on one of the first rigid support member and the second rigid support member and a corresponding opening on the other of the first rigid support member and the second rigid support member.

10. A semiconductor dice testing apparatus comprising:

a first rigid support member and a second rigid support member for receiving a plurality of semiconductor dice on a wafer therebetween, one of the first rigid support member and second rigid support member including a single cavity for retaining the plurality of semiconductor dice on a wafer therein during testing;

a plurality of contact members formed on the first rigid support member for communicating with electrical connectors for connecting to external test circuitry;

a single biasing assembly including a single floating platform having a preselected area substantially sized to correspond with the single cavity and an elastomeric member disposed on the second rigid support member, the single biasing assembly sized for uniformly biasing the plurality of semiconductor dice on a wafer towards the plurality of contact members, the single floating platform directly supporting the wafer with the elastomeric member sandwiched between the single floating platform and the second rigid support member.

11. The apparatus as claimed in claim 10, further comprising an alignment device for aligning the first rigid support member and the second rigid support member with one another.

12. The apparatus as claimed in claim 10, further comprising an alignment device including a dowel on one of the first rigid support member and second rigid support member and a corresponding opening on the other of the first rigid support member and the second rigid support member.

13. A testing apparatus for semiconductor dice in wafer form comprising:

a first rigid support member and a second rigid support member for receiving a plurality of semiconductor dice on a wafer therebetween, one of the first rigid support member and the second rigid support member including a single cavity for retaining the plurality of semiconductor dice on a wafer therein during testing;

a plurality of contact members formed on the first rigid support member for communicating with electrical connectors for connecting to external test circuitry;

a single biasing assembly including a single floating platform having a preselected area substantially sized to correspond with the single cavity and an elastomeric member disposed on the second rigid support member, the single biasing assembly sized for uniformly biasing the plurality of semiconductor dice on a wafer towards the plurality of contact members, the single floating platform directly supporting the wafer with the elastomeric member sandwiched between the single floating platform and the second rigid support member.

14. The apparatus as claimed in claim 13, further comprising an alignment device for aligning the first rigid support member and the second rigid support member with one another.

15. The apparatus as claimed in claim 13, further comprising an alignment device including a dowel on one of the first rigid support member and the second rigid support member and a corresponding opening on the other of the first rigid support member and the second rigid support member.