Isolation Buffers With Controlled Equal Time Delays

• US 20070103183A1
• Filed: 12/24/2006
• Published: 05/10/2007
• Est. Priority Date: 10/23/2003
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles
• Granted Patent: US 7,362,092 B2
• Time in Patent Office: Days
• US Class Current: 324/754.70
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: H03H 11/126 using a single operational amplifier H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03H 11/265 with adjustable delay

Abstract

A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffer to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch. A wafer test system can be configured using the isolation buffers having equal delays to enable concurrently connecting one tester channel to multiple wafer test probes.

Claims

1-23. -23. (canceled)

24. An apparatus for use in testing a plurality of electronic devices, the apparatus comprising:

a signal line connectable to a communications channel from a tester configured to control testing of the electronic devices;

a first variable delay isolation buffer comprising;

a first signal input connected to the signal line,

a first signal output connected to a first probe for contacting a first one of the electronic devices, and

a first variable delay control input for selectively varying a delay caused by the first variable delay isolation buffer in a signal traveling from the first signal input to the first signal output; and

a delay control circuit having an output providing the first variable delay control input of the first variable delay isolation buffer, the delay control circuit setting a delay control voltage potential at its output to control delay through the first variable delay isolation buffer to substantially match delay through a time delay reference.

25. The apparatus of claim 24 further comprising a second variable delay isolation buffer comprising:

a second signal input connected to the signal line,

a second signal output connected to a second probe for contacting a second of the electronic devices, and

a second variable delay control input for selectively varying a delay caused by the second variable delay isolation buffer in a signal traveling from the second signal input to the second signal output,

wherein the output of the delay control circuit is provided to the second variable delay control input of the second variable delay isolation buffer to control delay through the second variable delay isolation buffer to substantially match delay through the time delay reference.

26. The apparatus of claim 24, wherein the delay control circuit comprises:

a reference delay line;

a reference buffer having a signal input, a variable delay control input, and an output; and

a phase comparator having a first input connected to the reference delay line, a second input connected to the output of the reference buffer, and an output connected to the variable delay control input of the reference buffer and providing the output of the delay control circuit.

27. The apparatus of claim 26, wherein:

the delay control circuit further comprises a loop filter,

the output of the phase comparator being connected to the variable delay control input of the reference buffer through the loop filter, and

the output of the phase comparator providing the output of the delay control circuit through the loop filter.

28. The apparatus of claim 26, wherein the first variable delay isolation buffer and the reference buffer are fabricated on a single integrated circuit die.

29. The apparatus of claim 26, wherein the delay control circuit further comprises:

an oscillator connected by the reference delay line to the first input of the phase comparator and by the reference buffer to the second input of the phase comparator; and

a loop filter connecting the output of the phase comparator to the variable delay control input of the reference buffer, the output of the phase comparator providing the output of the delay control circuit through the loop filter.

30. The apparatus of claim 29, wherein:

the variable delay control input of the reference buffer and the first variable delay control input of the first isolation buffer each comprise a high level voltage input line and a low level voltage input line,

a system voltage comprises a system high voltage and a system low voltage power supply, and

the loop filter connects the phase comparator output to the high and low level voltage input lines of the reference buffer and the first variable delay isolation buffer, the loop filter comprising a means for integrating and centerlining the phase comparator output to provide an integrated signal on the high level voltage line relative to the high voltage power supply and an integrated signal on the low level voltage line relative to the low voltage power supply, so that the integrated signals on the high and low level voltage lines are centered between the high and low level voltage power supplies.

31. The apparatus of claim 30, wherein the means for integrating and centerlining comprises:

a first resistor comprising a first terminal connected to the output of the phase comparator, and a second terminal;

a second resistor comprising a first terminal connected to a system high voltage power supply line to receive the system high voltage power supply, the second resistor further comprising a second terminal;

a first capacitor;

a first amplifier having a noninverting (+) input connected to the second terminal of the first and second resistors, an inverting (−

) input, and an output connected to the high voltage input lines of the reference buffer and the first variable delay isolation buffer,

wherein the output of the first amplifier is fed back to its inverting (−

) input through the first capacitor;

a third resistor comprising a first terminal connected to the output of the phase comparator, the third resistor further comprising a second terminal;

a fourth resistor comprising a first terminal connected to a system low voltage power supply line to receive a system low voltage potential, the fourth resistor further comprising a second terminal;

a second capacitor; and

a second amplifier having an inverting (−

) input connected to the second terminal of the third resistor, a non-inverting (+) input connected to the second terminal of the fourth resistor, and an output connected to the low voltage input lines of the reference buffer and the first variable delay isolation buffer,

wherein the output of the second amplifier is fed back to its inverting (−

) input through the second capacitor.

32. The apparatus of claim 26, wherein:

the first variable delay isolation buffer comprises;

a first inverter having a variable delay control input receiving the control voltage potential as varied from a system voltage; and

a second inverter connected in series with the first inverter, the second inverter having a power supply input connected to receive the system voltage; and

the reference buffer comprises;

a third inverter having a variable delay control input receiving the control voltage potential as varied from the system voltage; and

a fourth inverter connected in series with the third inverter, the fourth inverter having a power supply input connected to receive the system voltage.

33. The apparatus of claim 24, further comprising additional buffers each having a signal input connected to the first signal output of the first variable delay isolation buffer, wherein an output of a first of the additional buffers is connected to the first probe, and an output of a second of the additional buffers is connected to a second probe for contacting a second of the electronic devices.

34. The apparatus of claim 33, wherein the additional buffers and the first variable delay isolation buffer each comprises a CMOS inverter.

35. The apparatus of claim 33, wherein the additional buffers comprise driver buffers.

36. The apparatus of claim 24, wherein the first variable delay isolation buffer comprises a differential amplifier and a variable current sink providing the variable delay control input.

37. The apparatus of any of claims 24-36, wherein the apparatus comprises a circuit assembly configured to be disposed between the tester and the electronic devices.

38. The apparatus of any of claims 24-36, wherein the apparatus comprises a probe card comprising an electrical interface for connecting to a plurality of communications channels to the tester and a plurality of probes for contacting the electronic devices.