Dual path redundancy with stacked transistor voting

• US 20070103185A1
• Filed: 11/03/2005
• Published: 05/10/2007
• Est. Priority Date: 11/03/2005
• Status: Abandoned Application

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Friedman, Mark
• Application Number:
  US11/266,447
• Publication Number:
  US 20070103185A1
• Time in Patent Office: Days
• US Class Current: 326/14
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/007 Fail-safe circuits

Abstract

A method of operation and an apparatus for radiation hardening a combinational logic circuit are presented. A section of logic that is to be radiation hardened is identified. An entire logic circuit or a portion of the logic circuit may be radiation hardened. Once the section of logic is identified, a Field Effect Transistor (FET) is duplicated so as to create a voter FET. The voter FET is coupled with an original node (or signal) and a duplicated node (or signal). If a radiation event strikes either the original node or the duplicated node, the voter FET will prevent an upset from propagating to down stream logic by preventing a conduction path through the voter FET. Additionally, all of the circuitry that was duplicated in order to create the duplicated node may also undergo a radiation event without causing an upset to propagate to downstream logic.

Claims

1. A method of radiation hardening a section of combinational logic circuitry comprising upstream logic coupled to a logic gate, the logic gate receiving a first input signal, and the logic gate comprising a first Field Effect Transistor (FET), the first FET having a gate, a source, and a drain, the method comprising:

coupling the first FET to a second FET, the second FET having a gate, a source, and a drain, the drain of the first FET coupled to the drain of the second FET so as to create a voter FET, the source of the first FET being a source of the voter FET, and the drain of the second FET being a drain of the voter FET; and

duplicating the first input signal so as to create a second input signal, the gate of the first FET coupled to receive the first input signal, and the gate of the second FET coupled to receive the second input signal.

2. The method of claim 1, further comprising creating a duplicate of the section of logic circuitry that is to be radiation hardened.

3. The method of claim 2, wherein the second input signal is output from the duplicate.

4. The method as in claim 1, wherein the voter FET allows a conduction path between the drain of the voter FET and the source of the voter FET only when the first and second input signals have an equivalent signal level.

5. The method as in claim 4, wherein the first and second FETs are a p-type FET (pFET).

6. The method as in claim 4, wherein the first and second FETs are an n-type FET (nFET).

7. The method as in claim 4, wherein the equivalent signal level is at voltage level that allows the first and second FETs to create the conduction channel between the respective sources and drains of the first and second FETs.

8. A method of operating a radiation hardened logic circuit, the logic circuit comprising a dual input voter Field Effect Transistor (FET), the voter FET comprising first and second FETs, the first and second FETs each having a gate, a source, and a drain, the drain of the first FET coupled to the source of the second FET, the gate of the first FET being a first input of the voter FET, and the gate of the second FET being a second input of the voter FET, the method comprising:

duplicating an original signal within the logic circuit so as to create a duplicated signal, the original signal being on a first duplicated node, and the duplicated signal being on a second duplicated node;

biasing the first input of the voter FET with the original signal;

biasing the second input of the voter FET with the duplicated signal;

opening a conduction path between the drain and the source of the voter FET; and

when a radiation event occurs on one of the duplicated nodes, closing the conduction path between the drain and the source of the voter FET.

9. The method of claim 8, wherein the radiation event is a Single Event Transient (SET) type.

10. The method of claim 8, wherein the first and second FETs are a p-type FET (pFET).

11. The method of claim 8, wherein the first and second FETs are an n-type FET (nFET).

12. The method of claim 8, wherein opening the conduction path further comprises:

adjusting the voltage level of the original signal so as to turn on the first FET; and

adjusting the voltage level of the duplicated signal so as to turn on the second FET.

13. The method of claim 12, wherein closing the conduction path further comprises adjusting the voltage level of the original signal so as to turn off the first FET.

14. The method of claim 12, wherein closing the conduction path further comprises adjusting the voltage level of the duplicated signal so as to turn off the second FET.

15. The method of claim 8, further comprising:

when the logic circuit recovers from the radiation event, re-opening the conduction path between the drain and the source of the voter FET.

16. The method of claim 8, wherein the upset on one of the duplicated nodes occurs on the first duplicated node.

17. The method of claim 8, wherein the upset on one of the duplicated nodes occurs on the second duplicated node.

18. A radiation hardened logic gate, the logic gate comprising:

first and second p-type Field Effect Transistors (pFETs) each having a gate, a source, and a drain, the drain of the first pFET coupled to the source of the second pFET so as to create a first voter pFET, the source of the first pFET being the source of the first voter pFET, the drain of the second pFET being the drain of the first voter pFET, and the gates of the first and second pFETs being respective first and second inputs of the first voter pFET; and

first and second n-type Field Effect Transistors (nFETs) each having a gate, a source, and a drain, the drain of the first nFET coupled to the source of the second nFET so as to create a first voter nFET, the source of the first nFET being the source of the first voter nFET, the drain of the second nFET being the drain of the first voter nFET, the gates of the first and second nFETs being respective first and second inputs of the first voter nFET, and the drain of the first voter nFET coupled to the drain of the second voter pFET.

19. The logic gate as in claim 18, wherein the first inputs of the first voter nFET and pFET are coupled to receive a first input signal, the second inputs of the first voter nFET and pFET are coupled to receive a second input signal, and the drain of the first voter nFET being an output of the logic gate thereby allowing the logic gate, in operation, to perform a logical NOT operation.

20. The logic gate as in claim 19, wherein the first and second input signals are duplicated signals, the logic gate performing the logical NOT operation when the first and second input signals are equivalent.

21. The logic gate as in claim 18, further comprising:

third and fourth pFETs each having a gate, a source, and a drain, the drain of the third pFET coupled to the source of the fourth pFET so as to create a second voter pFET, the source of the third pFET being the source of the second voter pFET, the drain of the fourth pFET being the drain of the second voter pFET, the gates of the third and fourth pFETs being respective first and second inputs of the second voter pFET, and the drain of the second voter pFET coupled to the source of the first voter pFET; and

third and fourth nFETs each having a gate, a source, and a drain, the drain of the third nFET coupled to the source of the fourth nFET so as to create a second voter nFET, the source of the third nFET being the source of the second voter nFET, the drain of the fourth nFET being the drain of the second voter nFET, the gates of the third and fourth nFETs being respective first and second inputs of the second voter nFET, and the drain of the second voter nFET coupled to the drain of the first voter nFET.

22. The logic gate as in claim 21, wherein the first inputs of the first voter nFET and pFET are coupled to receive a first input signal, the second inputs of the first voter nFET and pFET are coupled to receive a second input signal, the first inputs of the second voter nFET and pFET are coupled to receive a third input signal, the second inputs of the second voter nFET and pFET are coupled to receive a fourth input signal, and the drain of the first voter nFET being an output of the logic gate thereby allowing the logic gate, in operation, to perform a logical NOR operation.

23. The logic gate as in claim 22, wherein first and second input signals are first duplicated signals, the third and fourth input signals are second duplicated signals, the logic gate performing the logical NOR operation when the first and second input signals are equivalent and the third and fourth input signals are equivalent.

24. The logic gate as in claim 18, further comprising:

third and fourth pFETs each having a gate, a source, and a drain, the drain of the third pFET coupled to the source of the fourth pFET so as to create a second voter pFET, the source of the third pFET being the source of the second voter pFET, the drain of the fourth pFET being the drain of the second voter pFET, the gates of the third and fourth pFETs being respective first and second inputs of the second voter pFET, and the drain of the second voter pFET coupled to the drain of the first voter pFET; and

third and fourth nFETs each having a gate, a source, and a drain, the drain of the third nFET coupled to the source of the fourth nFET so as to create a second voter nFET, the source of the third nFET being the source of the second voter nFET, the drain of the fourth nFET being the drain of the second voter nFET, the gates of the third and fourth nFETs being respective first and second inputs of the second voter nFET, and the source of the second voter nFET coupled to the drain of the first voter nFET.

25. The logic gate as in claim 24, wherein the first inputs of the first voter nFET and pFET are coupled to receive a first input signal, the second inputs of the first voter nFET and pFET are coupled to receive a second input signal, the first inputs of the second voter nFET and pFET are coupled to receive a third input signal, the second inputs of the second voter nFET and pFET are coupled to receive a fourth input signal, and the drain of the first voter nFET being an output of the logic gate thereby allowing the logic gate, in operation, to perform a logical NAND operation.

26. The logic gate as in claim 25, wherein first and second input signals and the third and fourth input signals are duplicated signals, the logic gate performing the logical NAND operation when the first and second input signals are equivalent and the third and fourth input signals are equivalent.