Switchable PLL circuit

• US 20070103214A1
• Filed: 11/07/2006
• Published: 05/10/2007
• Est. Priority Date: 11/08/2005
• Status: Active Grant

• Current Assignee: InterDigital Madison Patent Holdings (InterDigital, Inc.)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Drexler, Michael, Schaefer, Ralf-Detlef
• Granted Patent: US 7,576,576 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/143 by switching the reference signal of the phase-locked loop
• CPC Class Codes: H03L 7/22 using more than one loop

Abstract

An electronic circuit includes a first and a second PLL stage (PLL1, PLL2) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input signal (IN). When in parallel, only the second PLL circuit (PLL2) is actively supplying a clock signal to the output of the electronic circuit. The first PLL circuit (PLL1) continues trying to lock onto the input signal (IN). A lock detector (LD) monitors the locking status of the first PLL circuit (PLL1) to the input signal (IN) and, upon locking, sets switches (S1, S2) to couple the output of the first PLL circuit (PLL1) to the input of the second PLL circuit (PLL2), and to couple the output of the second PLL circuit (PLL2) to the input of the first PLL circuit (PLL1).

Claims

1. An electronic circuit with a first PLL circuit including a first phase comparator and a first controllable oscillator, with a second PLL circuit including a second phase comparator and a second controllable oscillator, wherein an input signal is supplied to an input of the first PLL circuit, wherein the input signal or the output of the first PLL circuit is selectively supplied to an input of the second PLL circuit, and wherein the output of the second PLL circuit is the single output of the circuit.

2. The electronic circuit of claim 1, wherein the output of the first or the second PLL circuit is selectively connected to an input of the first PLL circuit (PLL1).

3. The electronic circuit of claim 2, wherein a first switch is provided for selectably connecting the output of the first or the second PLL circuit to an input of the first PLL circuit.

4. The electronic circuit of claim 2, wherein a second switch is provided for selectably connecting the output of the first PLL circuit or the input signal to an input of the second PLL circuit.

5. The electronic circuit of claim 1, wherein a lock detection circuit is provided which detects locking of the respective input signal to the output signal of the first controllable oscillator and, in case the input signal is locked to the output signal of the first controllable oscillator, controls the first and the second switch such that the output signal of the first PLL circuit is supplied to an input of the second PLL circuit and the output signal of the second PLL circuit is supplied to an input of the first PLL circuit.

6. The electronic circuit of claim 1, wherein the first PLL circuit further includes a first filter and/or the second PLL circuit further includes a second filter.

7. The electronic circuit of claim 1, wherein the first controllable oscillator has a pulling range that is smaller than that of the second controllable oscillator.

8. The electronic circuit of claim 1, wherein frequency dividers are provided between the input terminal and the first phase comparator, the output of the first controllable oscillator and respective inputs of the first and the second switch, and/or the output of the second controllable oscillator and the respective inputs of the second phase comparator and the first switch.

9. A method for operating an electronic circuit according to claim 1 including the steps of:

supplying an input signal to the inputs of a first and a second PLL circuit;

feeding back the signal of respective controllable oscillators of the first and the second PLL circuit to respective first and second phase comparators of the respective first and second PLL circuit; and

monitoring the lock status of the first PLL circuit with regard to the input signal in a lock detector.

10. The method of claim 9, further including the step of

supplying the output signal of the first PLL circuit to an input of the second PLL circuit, and the output signal of the second PLL circuit to an input of the first PLL circuit, when the first PLL circuit is locked onto the input signal.