Method for an element using two resist layers

• US 20070103379A1
• Filed: 11/10/2005
• Published: 05/10/2007
• Est. Priority Date: 11/10/2005
• Status: Active Grant

• Current Assignee: RCD Technology Corporation
• Original Assignee: SQUARE 1 BANK
• Inventors: Garby, Sandra, Oberle, Robert
• Granted Patent: US 7,388,542 B2
• Time in Patent Office: Days
• US Class Current: 343/895
• CPC Class Codes: H01Q 1/2208 associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems methods or arrangements for sensing record carriers, e.g. for reading patterns G06K7/00; record carrier for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H01Q 1/36 Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewithH01Q1/08, H01Q1/14 take precedence
• CPC Class Codes: H01Q 7/00 Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
• CPC Class Codes: H05K 1/095 for polymer thick films, i.e. having a permanent organic polymeric binder
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 2201/0347 Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias reinforcing the conductive pattern H05K3/24
• CPC Class Codes: H05K 2203/054 Continuous temporary metal layer over resist, e.g. for selective electroplating
• CPC Class Codes: H05K 2203/0574 Stacked resist layers used for different processes
• CPC Class Codes: H05K 2203/175 Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
• CPC Class Codes: H05K 3/048 using a lift-off resist pattern or a release layer pattern
• CPC Class Codes: H05K 3/242 characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
• CPC Class Codes: H05K 3/246 Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating
• CPC Class Codes: Y10T 29/49016 Antenna or wave energy "plumbing" making

Abstract

A two resist layer process allows a seed layer to be used to electroplate a conductive layer of an element in a way that a portion of the seed layer can be removed.

Claims

1. A method of forming an element, comprising:

forming a first resist layer on top of a substrate;

forming a seed layer on top of at least a portion of the first resist layer;

forming a second resist layer over a portion of the seed layer;

electroplating a conductive layer over exposed portions of the seed layer; and

removing the first and second resist.

2. The method of claim 1, wherein the element is an antenna.

3. The method of claim 1, wherein the seed layer has a coil pattern.

4. The method of claim 1, wherein after the removing step the conductive layer includes at least two electrically isolated regions.

5. The method of claim 1, wherein the electrically isolated regions are individual antenna elements.

6. The method of claim 1, wherein the seed layer comprises a conductive ink layer.

7. The method of claim 1, wherein the removing step comprises using a solvent to remove the first and second resist layers.

8. The method of claims 1, wherein the portion of the seed layer on top of the first resist layer electrically connects a bus bar to an antenna during the electroplating step.

9. The method of claim 1, wherein the portion of seed layer on top of the first resist layer shorts together portions of an antenna coil during the electroplating step.

10. The method of claim 1, wherein the portion of the seed layer on top of the first resist layer shorts together portions of a dipole antenna

19. The element of claim 11, wherein the element has an exposed seed layer portion.

11. An element constructed by the process of:

forming a first resist layer on top of a substrate;

forming a seed layer on top of at least a portion of the first resist layer;

forming a second resist layer over a portion of the seed layer;

electroplating a conductive layer over exposed portions of the seed layer; and

removing the first and second resist.

12. The element of claim 11, wherein the element is an antenna.

13. The element of claim 11, wherein the seed layer has a coil pattern.

14. The element of claim 11, wherein after the removing step the conductive layer includes at least two electrically isolated regions.

15. The element of claim 11, wherein the seed layer comprises a conductive ink layer.

16. The element of claim 11, wherein the removing step comprises using a solvent to remove the first and second resist layers.

17. The element of claims 11, wherein the portion of the seed layer on top of the first resist layer electrically connects a bus bar to an antenna during the electroplating step.

18. The element of claim 11, wherein the portion of seed layer on top of the first resist layer shorts together portion of an antenna coil during the electroplating step.

20. An RFID antenna constructed by the process of:

forming a first resist layer on top of a substrate;

forming a seed layer on top of at least a portion of the first resist layer;

forming a second resist layer over a portion of the seed layer;

electroplating a conductive layer over exposed portions of the seed layer; and

removing the first and second resist.

21. The RFID antenna of claim 20, wherein the element has an exposed seed layer portion.