Memory system

• US 20070103992A1
• Filed: 11/08/2006
• Published: 05/10/2007
• Est. Priority Date: 11/10/2005
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Suzuki, Kazuhiro, Yoshioka, Daisuke, Ishimoto, Takeshi, Sumino, Jun, Kamimura, Kazuto, Sakui, Koji
• Granted Patent: US 7,694,066 B2
• Time in Patent Office: Days
• US Class Current: 365/185.330
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A memory system including a nonvolatile semiconductor storage device includes: a nonvolatile memory unit that includes a first data area in which data is frequently rewritten and a second data area in which data is hardly rewritten; and a control unit. The control unit sequentially selects logical block addresses in the second data area in which data is hardly rewritten and updates physical block addresses at new rewriting destinations in the first data area in which data is frequently rewritten to physical block addresses corresponding to the logical block addresses selected.

Claims

1. A memory system including a nonvolatile semiconductor storage device, comprising:

a nonvolatile memory unit that includes a first data area in which data is frequently rewritten and a second data area in which data is hardly rewritten; and

a control unit, wherein

the control unit sequentially selects logical block addresses in the second data area in which data is hardly rewritten and updates physical block addresses at new rewriting destinations in the first data area in which data is frequently rewritten to physical block addresses corresponding to the logical block addresses selected.

2. A memory system according to claim 1, wherein the control unit copies data stored in the logical block addresses in the second data area in which data is hardly rewritten to an erased block and, then, erases a block at a copy source.

3. A memory system according to claim 2, wherein the control unit provides identification flags in at least one of the logical block addresses that store data hardly rewritten and the logical block addresses that store data frequently rewritten.

4. A memory system according to claim 1, wherein the control unit immediately writes, after erasing a logical block address, the erased logical block address in the erased block and sequentially rewrites blocks to be rewritten in accordance with the erased logical block address.

5. A memory system according to claim 2, wherein the control unit immediately writes, after erasing a logical block address, the erased logical block address in the erased block and sequentially rewrites blocks to be rewritten in accordance with the erased logical block address.

6. A memory system including a nonvolatile semiconductor storage device, comprising:

a nonvolatile memory unit that includes a first data area in which data is frequently rewritten and a second data area in which data is hardly rewritten; and

a control unit that sequentially selects logical block addresses in the second data area in which data is hardly rewritten and updates physical block addresses at new rewriting destinations in the first data area in which data is frequently rewritten to physical block addresses corresponding to the logical block addresses selected, wherein

the control unit is capable of performing, in performing Wear-leveling control for preventing rewriting from being concentrated in a specific physical address block, Passive-wear-leveling control for leaving a physical address block not rewritten as it is and Active-wear-leveling control for rewriting even a physical address block not rewritten such that the numbers of times of rewriting of all physical address blocks are averaged, and

system selection for the Passive-wear-leveling control and the Active-wear-leveling control or condition setting values of both the kinds of Wear-leveling are stored in the nonvolatile memory unit.

7. A memory system according to claim 6, wherein the control unit selects, when data not frequently rewritten is stored. in more than half blocks of the nonvolatile memory unit, the Active-wear-leveling control system and selects, when data frequently rewritten is stored in more than half blocks of the nonvolatile memory unit, the Passive-wear-leveling control system.

8. A memory system according to claim 6, further comprising a page buffer, wherein

the system selection for the Passive-wear-leveling control and the Active-wear-leveling control or the condition setting values of both the kinds of Wear-leveling are stored in a first page of the nonvolatile memory unit and automatically read out to the page buffer when a power supply is turned on.

9. A memory system according to claim 7, further comprising a page buffer, wherein

the system selection for the Passive-wear-leveling control and the Active-wear-leveling control or the condition setting values of both the kinds of Wear-leveling are stored in a first page of the nonvolatile memory unit and automatically read out to the page buffer when a power supply is turned on.

10. A memory system according to claim 6, wherein it is possible to arbitrarily set the system selection for the Passive-wear-leveling control and the Active-wear-leveling control and the condition setting values of both the kinds of Wear-leveling.

11. A memory system according to claim 8, wherein it is possible to arbitrarily set the system selection for the Passive-wear-leveling control and the Active-wear-leveling control and the condition setting values of both the kinds of Wear-leveling.

12. A memory system according to claim 6, wherein the control unit copies data stored in the logical block addresses in the second data area in which data is hardly rewritten to an erased block and, then, erases a block at a copy source.

13. A memory system according to claim 12, wherein the control unit provides identification flags in at least one of the logical block addresses that store data hardly rewritten and the logical block addresses that store the data frequently rewritten.

14. A memory system according to claim 6, wherein the control unit immediately writes, after erasing a logical block address, the erased logical block address in the erased block and sequentially rewrites blocks to be rewritten in accordance with the erased logical block address.

15. A memory system according to claim 6, wherein the nonvolatile semiconductor storage device includes a NAND flash memory in which plural rewritable nonvolatile memory cells are connected in series.