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Multi-Bit-Per-Cell Flash EEprom Memory with Refresh

  • US 20070104004A1
  • Filed: 01/05/2007
  • Published: 05/10/2007
  • Est. Priority Date: 09/08/1997
  • Status: Active Grant
First Claim
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1. A non-volatile semiconductor memory comprising:

  • an array of memory cells;

    drivers and decoders coupled to apply voltages to the array to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage that identifies a multibit data value written in the memory cell;

    an error detection circuit that detects errors in threshold voltages of memory cells storing data, wherein in response to detecting an error in the threshold voltage of a memory cell, the error detection circuit signals for a refresh operation; and

    a control circuit coupled to control the drivers and decoders, wherein during the refresh operation, the control circuit writes a corrected threshold voltage that corrects the error that the error detection circuit detected.

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