Method and apparatus for reducing standby current in a dynamic random access memory during self refresh

• US 20070104005A1
• Filed: 11/09/2005
• Published: 05/10/2007
• Est. Priority Date: 11/09/2005
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Bowyer, Stephen, Zieleman, Jan
• Granted Patent: US 7,366,047 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense amplifier, and a control circuit. The control circuit is configured to isolate the sense amplifier from at least one of the first dynamic random access memory cell and the second dynamic random access memory cell in an idle state and to couple the sense amplifier to only the second dynamic random access memory cell to be refreshed in a refresh state.

Claims

1. A dynamic random access memory, comprising:

a first dynamic random access memory cell;

a second dynamic random access memory cell to be refreshed;

a sense amplifier;

a control circuit configured to isolate the sense amplifier from at least one of the first dynamic random access memory cell and the second dynamic random access memory cell in an idle state and to couple the sense amplifier to only the second dynamic random access memory cell to be refreshed in a refresh state.

2. The dynamic random access memory of claim 1, comprising:

a first circuit coupled between the sense amplifier and the first dynamic random access memory cell; and

a second circuit coupled between the sense amplifier and the second dynamic random access memory cell.

3. The dynamic random access memory of claim 2, wherein the first circuit is configured to isolate the sense amplifier from the first dynamic random access memory cell and the second circuit is configured to isolate the sense amplifier from the second dynamic random access memory cell.

4. The dynamic random access memory of claim 1, wherein the control circuit is configured to isolate the sense amplifier from the first dynamic random access memory cell in the idle state and maintain isolation of the sense amplifier from the first dynamic random access memory cell between the idle state and the refresh state to refresh the second dynamic random access memory cell.

5. The dynamic random access memory of claim 4, wherein the control circuit is configured to connect the sense amplifier to the first dynamic random access memory cell in a pre-charge time between the idle state and the refresh state to refresh the first dynamic random access memory cell.

6. A dynamic random access memory, comprising:

a first segment of first dynamic random access memory cells including first bit lines;

a second segment of second dynamic random access memory cells including second bit lines;

sense amplifiers;

a first circuit configured to isolate the sense amplifiers from the first bit lines;

a second circuit configured to isolate the sense amplifiers from the second bit lines;

a control circuit configured to isolate the sense amplifiers from the first bit lines via the first circuit in an idle state and to maintain isolation of the sense amplifiers from the first bit lines via the first circuit and connect the sense amplifiers to the second bit lines via the second circuit to refresh second dynamic random access memory cells and to connect the sense amplifiers to the first bit lines via the first circuit and isolate the sense amplifiers from the second bit lines via the second circuit to refresh first dynamic random access memory cells.

7. The dynamic random access memory of claim 6, wherein the control circuit is configured to isolate the sense amplifiers from the second bit lines via the second circuit in the idle state.

8. The dynamic random access memory of claim 7, wherein the control circuit is configured to connect the sense amplifiers to the first bit lines and provide a pre-charge time prior to activating an activation signal to refresh first dynamic random access memory cells.

9. The dynamic random access memory of claim 6, wherein the control circuit is configured to connect the sense amplifiers to the second bit lines via the second circuit in the idle state and to connect the sense amplifiers to the first bit lines and provide a pre-charge time prior to activating an activation signal and isolating the sense amplifiers from the second bit lines to refresh first dynamic random access memory cells.

10. The dynamic random access memory of claim 9, wherein the control circuit is configured to connect the sense amplifiers to the second bit lines in response to deactivation of the activation signal and to provide a post conditioning pre-charge time prior to isolating the sense amplifiers from the first bit lines in the idle state.

11. A dynamic random access memory, comprising:

first dynamic random access memory cells;

second dynamic random access memory cells;

a sense amplifier;

a first pre-charge circuit configured to pre-charge first bit lines corresponding to the first dynamic random access memory cells;

a second pre-charge circuit configured to pre-charge second bit lines corresponding to the second dynamic random access memory cells;

a first isolation circuit configured to isolate the sense amplifier from the first pre-charge circuit;

a second isolation circuit configured to isolate the sense amplifier from the second pre-charge circuit;

a control circuit configured to isolate the sense amplifier from the first pre-charge circuit via the first isolation circuit in an idle state and to maintain isolation of the sense amplifier from the first pre-charge circuit via the first isolation circuit and connect the sense amplifier to the second pre-charge circuit via the second isolation circuit to refresh second dynamic random access memory cells and to connect the sense amplifier to the first pre-charge circuit via the first isolation circuit and isolate the sense amplifier from the second pre-charge circuit via the second isolation circuit to refresh first dynamic random access memory cells.

12. The dynamic random access memory of claim 11, wherein the control circuit is configured to isolate the sense amplifier from the second pre-charge circuit via the second isolation circuit in the idle state and to connect the sense amplifier to the first pre-charge circuit via the first isolation circuit and provide a pre-charge time prior to activating an activation signal to refresh first dynamic random access memory cells.

13. The dynamic random access memory of claim 11, wherein the control circuit is configured to connect the sense amplifier to the second pre-charge circuit in the idle state and to connect the sense amplifier to the first pre-charge circuit and provide a pre-charge time prior to activating an activation signal and isolating the sense amplifier from the second pre-charge circuit to refresh first dynamic random access memory cells.

14. The dynamic random access memory of claim 13, wherein the control circuit is configured to connect the sense amplifier to the second pre-charge circuit in response to deactivation of the activation signal and to provide a post conditioning pre-charge time prior to isolating the sense amplifier from the first pre-charge circuit.

15. The dynamic random access memory of claim 11, wherein each of the first and second dynamic random access memory cells is a single transistor single capacitor memory cell and the sense amplifier is a differential sense amplifier.

16. A dynamic random access memory, comprising:

means for isolating sense amplifiers from first bit lines that correspond to first dynamic random access memory cells;

means for isolating the sense amplifiers from second bit lines that correspond to second dynamic random access memory cells;

means for isolating the sense amplifiers from the first bit lines in the idle state;

means for maintaining isolation of the sense amplifiers from the first bit lines and connecting the sense amplifiers to the second bit lines to refresh second dynamic random access memory cells; and

means for connecting the sense amplifiers to the first bit lines and isolating the sense amplifiers from the second bit lines to refresh first dynamic random access memory cells.

17. The dynamic random access memory of claim 16, comprising:

means for isolating the sense amplifiers from the second bit lines in the idle state.

18. The dynamic random access memory of claim 17, comprising:

means for providing a pre-charge time between connecting the sense amplifiers to the first bit lines and activating an activation signal to refresh first dynamic random access memory cells.

19. The dynamic random access memory of claim 16, comprising:

means for connecting the sense amplifiers to the second bit lines in the idle state;

means for providing a pre-charge time between connecting the sense amplifiers to the first bit lines and activating an activation signal; and

means for isolating the sense amplifiers from the second bit lines based on activating the activation signal to refresh first dynamic random access memory cells.

20. The dynamic random access memory of claim 19, comprising:

means for connecting the sense amplifiers to the second bit lines in response to deactivation of the activation signal; and

means for providing a post conditioning pre-charge time between connecting the sense amplifiers to the second bit lines and isolating the sense amplifiers from the first bit lines.

21. A method for refreshing dynamic random access memory cells comprising:

isolating sense amplifiers from first bit lines that correspond to first dynamic random access memory cells during a pre-charge state;

maintaining isolation of the sense amplifiers from the first bit lines to refresh second dynamic random access memory cells;

connecting the sense amplifiers to second bit lines that correspond to the second dynamic random access memory cells to refresh the second dynamic random access memory cells;

connecting the sense amplifiers to the first bit lines to refresh the first dynamic random access memory cells; and

isolating the sense amplifiers from the second bit lines to refresh the first dynamic random access memory cells.

22. The method of claim 21, wherein isolating the sense amplifiers from the second bit lines comprises:

isolating the sense amplifiers from the second bit lines during the pre-charge state.

23. The method of claim 22, comprising:

activating an activation signal to refresh the first dynamic random access memory cells; and

providing a pre-charge time between connecting the sense amplifiers to the first bit lines and activating the activation signal.

24. The method of claim 21, comprising:

connecting the sense amplifiers to the second bit lines during the pre-charge state;

activating an activation signal to refresh the first dynamic random access memory cells;

providing a pre-charge time between connecting the sense amplifiers to the first bit lines and activating the activation signal; and

isolating the sense amplifiers from the second bit lines at the end of the pre-charge time to refresh first dynamic random access memory cells.

25. The method of claim 24, comprising:

deactivating the activation signal;

connecting the sense amplifiers to the second bit lines based on deactivation of the activation signal;

isolating the sense amplifiers from the first bit lines based on deactivation of the activation signal; and

providing a post conditioning pre-charge time between connecting the sense amplifiers to the second bit lines based on deactivation of the activation signal and isolating the sense amplifiers from the first bit lines based on deactivation of the activation signal.

26. A method for refreshing dynamic random access memory cells comprising:

precharging first bit lines that correspond to first dynamic random access memory cells during an idle state;

precharging second bit lines that correspond to second dynamic random access memory cells during the idle state;

isolating a sense amplifier from the first bit lines during the idle state;

maintaining isolation of the sense amplifier from the first bit lines to refresh one of the second dynamic random access memory cells;

connecting the sense amplifier to the second bit lines to refresh the one of the second dynamic random access memory cells;

isolating the sense amplifier from the second bit lines to refresh one of the first dynamic random access memory cells; and

connecting the sense amplifier to the first bit lines to refresh the one of the first dynamic random access memory cells.

27. The method of claim 26, wherein isolating the sense amplifier from the second bit lines comprises:

isolating the sense amplifier from the second bit lines in the idle state.

28. The method of claim 27, comprising:

activating an activation signal to refresh the one of the first dynamic random access memory cells; and

providing a pre-charge time between connecting the sense amplifier to the first bit lines and activating the activation signal to refresh the one of the first dynamic random access memory cells.

29. The method of claim 26, comprising:

connecting the sense amplifier to the second bit lines in the idle state.

30. The method of claim 29, comprising:

activating an activation signal to refresh the one of the first dynamic random access memory cells; and

providing a pre-charge time between connecting the sense amplifier to the first bit lines and isolating the sense amplifier from the second bit lines based on activating the activation signal.

31. The method of claim 30, comprising:

connecting the sense amplifier to the second bit lines based on deactivating the activation signal; and

providing a post conditioning pre-charge time between connecting the sense amplifier to the second bit lines based on deactivating the activation signal and isolating the sense amplifier from the first bit lines.