SILICIDED RECESSED SILICON

• US 20070105357A1
• Filed: 12/21/2006
• Published: 05/10/2007
• Est. Priority Date: 09/01/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Iyer, Ravi, Nejad, Hasan, Harnish, Justin, Haller, Gordon, Figura, Thomas, Meldrim, John
• Granted Patent: US 9,076,888 B2
• Time in Patent Office: Days
• US Class Current: 438/586
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823443 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

Claims

1. An integrated circuit including a metal silicide structure, the structure comprising a metal silicide filling at least a lower portion of a recess without voids, the metal silicide comprising a mixture of at least a first metal having a greater diffusivity in silicon than silicon has in the first metal and a second metal having a lesser diffusivity in silicon than silicon has in the second metal.

2. The integrated circuit of claim 1, wherein the recess comprises a trench formed within a semiconductor substrate.

3. The integrated circuit of claim 2, wherein the trench is lined with a thin dielectric layer, and the metal silicide comprises a word line for a memory array.

4. The integrated circuit of claim 1, wherein the recess defines an aspect ratio of greater than about 2:

1.

5. The integrated circuit of claim 1, wherein the recess defines an opening having a width between about 25 nm and 75 nm.

6. The integrated circuit of claim 1, wherein the metal silicide comprises nickel and cobalt.

7. The integrated circuit of claim 6, wherein about 70-90 at. % of metal in the metal silicide comprises nickel.

8. The integrated circuit of claim 7, wherein about 10-30 at. % of metal in the metal silicide comprises cobalt.

9. The integrated circuit of claim 1, wherein the first metal is selected from the group consisting of nickel, platinum and copper, and the second metal is selected from the group consisting of cobalt, titanium and tantalum.

10. A memory device comprising a recessed access device in a memory array, comprising:

a recess within a semiconductor substrate;

a thin dielectric layer lining the recess; and

a metal silicide filling at least a lower portion of the trench without voids.

11. The memory device of claim 10, wherein the metal silicide comprises at least two metals having opposite diffusivities relative to silicon.

12. The memory device of claim 10, wherein the metal silicide comprises a first metal selected from the group consisting of nickel, platinum and copper, and a second metal selected from the group consisting of cobalt, titanium and tantalum.

13. The memory device of claim 10, wherein the recessed access device shares a source with an adjacent recessed access device.

14. The memory device of claim 10, wherein the recess defines an opening having a width between about 25 nm and 75 nm.

15. The memory device of claim 10, wherein about 70-90 at. % of metal in the metal silicide comprises nickel.

16. The memory device of claim 15, wherein about 10-30 at. % of metal in the metal silicide comprises cobalt.