Scalable distributed memory and I/O multiprocessor systems and associated methods

• US 20070106833A1
• Filed: 06/06/2006
• Published: 05/10/2007
• Est. Priority Date: 05/10/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cheng, Kai, Wang, Wen-Hann, Rankin, Linda, Borkar, Nitin, Hofsheier, Richard, Pierce, Paul, Dermer, Gregory
• Granted Patent: US 7,343,442 B2
• Time in Patent Office: Days
• US Class Current: 710/317
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Claims

1. A multiprocessor system comprising:

at least one processing module;

at least one input/output module; and

an interconnect network to communicatively couple the at least one processing module with the at least one input/output module, the interconnect network including;

at least two bridges to send and receive transactions from the at least one input/output module and the at least one processing module; and

at least two crossbar switches to route the transactions over a bus between the at least two bridges.

2. The multiprocessor system of claim 1 wherein the at least two bridges support a point-to-point protocol.

3. The multiprocessor system of claim 2 wherein the at least two bridges manage a translation of the point-to-point protocol to a protocol of the interconnect network.

4. The multiprocessor system of claim 1 wherein the at least two crossbar switches comprise non-blocking switches having a plurality of ports.

6. The multiprocessor system of claim 1 wherein a clock for the at least two crossbar switches has a source that is independent of a clock for the at least one processing module.

7. The multiprocessor system of claim 1 wherein the at least one processing module comprises at least one processor, a memory and a memory controller.

8. The multiprocessor system of claim 7 wherein the at least one processing module includes four processors.

5. The multiprocessor system of 4 wherein the at least two crossbar switches support independent power/on and reset of the ports.

9. A multiprocessor system, comprising:

at least one processing module;

at least one input/output module;

one or more buses to communicatively couple the at least one processing module and the at least one input/output module;

at least one interconnect component coupled to the at least one processing module and the at least one input/output module, the interconnect component to support a protocol of the one or more buses between the at least one processing module and the at least one input/output module;

wherein the at least one interconnect component may be separate from both the at least one processing module and the at least one input/output module.

10. The multiprocessor system of claim 9 wherein the at least one interconnect component is included in at least one of the processing modules.

11. The multiprocessor system of claim 9 wherein the at least one interconnect component is included in at least one of the input/output modules.

12. The multiprocessor system of claim 9 wherein the at least one interconnect component comprises at least one bridge and a crossbar router.

13. The multiprocessor system of claim 9 wherein the at least one interconnect component manages a translation of a point-to-point protocol to a protocol of the one or more buses.

14. The multiprocessor system of claim 9 wherein the at least one processing module comprises at least one processor, a memory and a memory controller.

15. A integrated circuit comprising:

a crossbar router; and

a bridge communicatively coupled to the crossbar router, the bridge to packetize transactions between a processing module and an input/output module in a format that is compatible with the crossbar router.

16. The integrated circuit of claim 16 further comprising a plurality of mapping registers communicatively coupled to the bridge, the mapping registers to provide routing information for the bridge.

17. The integrated circuit of claim 16 further comprising:

at least one additional processing module; and

at least one DMA engine coupled to the crossbar router, the DMA engine to facilitate message-passing between the processing modules.

18. A method of operating a multiprocessor system including at least one processing module, at least one input/output module, and at least one interconnect network communicatively coupling the at least one processing module and the at least one input/output module, the method comprising:

the at least one interconnect network utilizing at least two bridges to send and receive transactions between the at least one processing module and the at least one input/output module; and

the at least one interconnect network utilizing at least two crossbar switches to route the transactions over a bus between the at least two bridges.

19. The method of claim 18, further comprising:

the at least one interconnect network utilizing the at least two bridges to support a point-to-point protocol.

20. The method of claim 19, further comprising:

the at least one interconnect network utilizing the at least two bridges to manage a translation of the point-to-point protocol to a protocol of the interconnect network.